SNLS341C March   2011  – March 2015 DP83848Q-Q1

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1  Pin Layout
    2. 3.2  Package Pin Assignments
    3. 3.3  Serial Management Interface
    4. 3.4  MAC Data Interface
    5. 3.5  Clock Interface
    6. 3.6  LED Interface
    7. 3.7  RESET
    8. 3.8  Strap Options
    9. 3.9  10 Mb/s and 100 Mb/s PMD Interface
    10. 3.10 Special Connections
    11. 3.11 Power Supply Pins
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics: DC
    6. 4.6 Electrical Characteristics: AC
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Auto-Negotiation
        1. 5.3.1.1 Auto-Negotiation Pin Control
        2. 5.3.1.2 Auto-Negotiation Register Control
        3. 5.3.1.3 Auto-Negotiation Parallel Detection
        4. 5.3.1.4 Auto-Negotiation Restart
        5. 5.3.1.5 Enabling Auto-Negotiation via Software
        6. 5.3.1.6 Auto-Negotiation Complete Time
      2. 5.3.2 Auto-MDIX
      3. 5.3.3 LED Interface
        1. 5.3.3.1 LEDs
        2. 5.3.3.2 LED Direct Control
      4. 5.3.4 Internal Loopback
      5. 5.3.5 BIST
      6. 5.3.6 Energy Detect Mode
    4. 5.4 Device Functional Modes
      1. 5.4.1 MII Interface
        1. 5.4.1.1 Nibble-wide MII Data Interface
        2. 5.4.1.2 Collision Detect
        3. 5.4.1.3 Carrier Sense
      2. 5.4.2 Reduced MII Interface
      3. 5.4.3 802.3u MII Serial Management Interface
        1. 5.4.3.1 Serial Management Register Access
        2. 5.4.3.2 Serial Management Access Protocol
        3. 5.4.3.3 Serial Management Preamble Suppression
      4. 5.4.4 PHY Address
        1. 5.4.4.1 MII Isolate Mode
      5. 5.4.5 Half Duplex vs. Full Duplex
      6. 5.4.6 Reset Operation
        1. 5.4.6.1 Hardware Reset
        2. 5.4.6.2 Software Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-Group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
        2. 5.5.1.2 100BASE-TX Receiver
          1. 5.5.1.2.1  Analog Front End
          2. 5.5.1.2.2  Digital Signal Processor
            1. 5.5.1.2.2.1 Digital Adaptive Equalization and Gain Control
            2. 5.5.1.2.2.2 Base Line Wander Compensation
          3. 5.5.1.2.3  Signal Detect
          4. 5.5.1.2.4  MLT-3 to NRZI Decoder
          5. 5.5.1.2.5  NRZI to NRZ
          6. 5.5.1.2.6  Serial to Parallel
          7. 5.5.1.2.7  Descrambler
          8. 5.5.1.2.8  Code-group Alignment
          9. 5.5.1.2.9  4B/5B Decoder
          10. 5.5.1.2.10 100BASE-TX Link Integrity Monitor
          11. 5.5.1.2.11 Bad SSD Detection
        3. 5.5.1.3 10BASE-T Transceiver Module
          1. 5.5.1.3.1  Operational Modes
            1. 5.5.1.3.1.1 Half Duplex Mode
            2. 5.5.1.3.1.2 Full Duplex Mode
          2. 5.5.1.3.2  Smart Squelch
          3. 5.5.1.3.3  Collision Detection and SQE
          4. 5.5.1.3.4  Carrier Sense
          5. 5.5.1.3.5  Normal Link Pulse Detection and Generation
          6. 5.5.1.3.6  Jabber Function
          7. 5.5.1.3.7  Automatic Link Polarity Detection and Correction
          8. 5.5.1.3.8  Transmit and Receive Filtering
          9. 5.5.1.3.9  Transmitter
          10. 5.5.1.3.10 Receiver
    6. 5.6 Memory
      1. 5.6.1 Register Definition
        1. 5.6.1.1 Basic Mode Control Register (BMCR)
        2. 5.6.1.2 Basic Mode Status Register (BMSR)
        3. 5.6.1.3 PHY Identifier Register #1 (PHYIDR1)
        4. 5.6.1.4 PHY Identifier Register #2 (PHYIDR2)
        5. 5.6.1.5 Auto-Negotiation Advertisement Register (ANAR)
        6. 5.6.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.6.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 5.6.1.8 Auto-Negotiate Expansion Register (ANER)
        9. 5.6.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
      2. 5.6.2 Extended Registers
        1. 5.6.2.1  PHY Status Register (PHYSTS)
        2. 5.6.2.2  False Carrier Sense Counter Register (FCSCR)
        3. 5.6.2.3  Receiver Error Counter Register (RECR)
        4. 5.6.2.4  100 Mb/s PCS Configuration and Status Register (PCSR)
        5. 5.6.2.5  RMII and Bypass Register (RBR)
        6. 5.6.2.6  LED Direct Control Register (LEDCR)
        7. 5.6.2.7  PHY Control Register (PHYCR)
        8. 5.6.2.8  10 Base-T Status/Control Register (10BTSCR)
        9. 5.6.2.9  CD Test and BIST Extensions Register (CDCTRL1)
        10. 5.6.2.10 Energy Detect Control (EDCR)
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 TPI Network Circuit
        2. 6.2.1.2 Clock IN (X1) Requirements
        3. 6.2.1.3 Power Feedback Circuit
        4. 6.2.1.4 Magnetics
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 MAC Interface (MII/RMII)
        2. 6.2.2.2 Termination Requirement
        3. 6.2.2.3 Recommended Maximum Trace Length
        4. 6.2.2.4 Calculating Impedance
      3. 6.2.3 Application Curve
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 PCB Layout Considerations
      2. 8.1.2 PCB Layer Stacking
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Power Supply Recommendations

The device Vdd supply pins should be bypassed with low impedance 0.1-μF surface mount capacitors. To reduce EMI, the capacitors should be places as close as possible to the component Vdd supply pins, preferably between the supply pins and the vias connecting to the power plane. In some systems it may be desirable to add 0-Ω resistors in series with supply pins, as the resistor pads provide flexibility if adding EMI beads becomes necessary to meet system level certification testing requirements. (See Figure 7-1) It is recommended the PCB have at least one solid ground plane and one solid Vdd plane to provide a low impedance power source to the component. This also provides a low impedance return path for non-differential digital MII and clock signals. A 10-μF capacitor should also be placed near the PHY component for local bulk bypassing between the Vdd and ground planes.

DP83848Q-Q1 psr_snls341.pngFigure 7-1 Vdd Bypass Layout