The number of applications requiring Ethernet connectivity continues to increase, driving Ethernet enabled devices into harsher environments.
The DP83848C/I/VYB/YB was designed to meet the challenge of these new applications with an extended temperature performance that goes beyond the typical Industrial temperature range. The DP83848C/I/VYB/YB is a highly reliable, feature rich, robust device which meets IEEE 802.3 standards over multiple temperature ranges from commercial to extreme temperatures. This device is ideally suited for harsh environments such as wireless remote base stations, automotive/transportation, and industrial control applications.
It offers enhanced ESD protection and the choice of an MII or RMII interface for maximum flexibility in MPU selection; all in a 48 pin package.
The DP83848VYB extends the leadership position of the PHYTER™ family of devices with a wide operating temperature range. The TI line of PHYTER transceivers builds on decades of Ethernet expertise to offer the high performance and flexibility that allows the end user an easy implementation tailored to meet these application needs.
Changes from D Revision (April 2013) to E Revision
Changes from C Revision (April 2013) to D Revision
DEVICE | TEMPERATURE RANGE | TEMPERATURE GRADE | |
---|---|---|---|
DP83848C | 0°C | 70°C | Commercial |
DP83848I | -40°C | 85°C | Industrial |
DP83848VYB | -40°C | 105°C | Extended |
DP83848YB | -40°C | 125°C | Extreme |
The DP83848VYB pins are classified into the following interface categories (each interface is described in the sections that follow):
NOTE
Strapping pin option. See Section 4.9 for strap definitions.
All DP83848VYB signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin.
VBH48A PIN # | PIN NAME | VBH48A PIN # | PIN NAME |
---|---|---|---|
1 | TX_CLK | 26 | LED_ACT/COL/AN_EN |
2 | TX_EN | 27 | LED_SPEED/AN1 |
3 | TXD_0 | 28 | LED_LINK/AN0 |
4 | TXD_1 | 29 | RESET_N |
5 | TXD_2 | 30 | MDIO |
6 | TXD_3/SNI_MODE | 31 | MDC |
7 | PWR_DOWN/INT | 32 | IOVDD33 |
8 | TCK | 33 | X2 |
9 | TDO | 34 | X1 |
10 | TMS | 35 | IOGND |
11 | TRST# | 36 | DGND |
12 | TDI | 37 | PFBIN2 |
13 | RD - | 38 | RX_CLK |
14 | RD + | 39 | RX_DV/MII_MODE |
15 | AGND | 40 | CRS/CRS_DV/LED_CFG |
16 | TD - | 41 | RX_ER/MDIX_EN |
17 | TD + | 42 | COL/PHYAD0 |
18 | PFBIN1 | 43 | RXD_0/PHYAD1 |
19 | AGND | 44 | RXD_1/PHYAD2 |
20 | RESERVED | 45 | RXD_2/PHYAD3 |
21 | RESERVED | 46 | RXD_3/PHYAD4 |
22 | AVDD33 | 47 | IOGND |
23 | PFBOUT | 48 | IOVDD33 |
24 | RBIAS | 49 | GNDPAD |
25 | CLK_OUT |
SIGNAL NAME | TYPE | PIN # | DESCRIPTION |
---|---|---|---|
MDC | I | 31 | MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. |
MDIO | I/O | 30 | MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor. |
SIGNAL NAME | TYPE | PIN # | DESCRIPTION |
---|---|---|---|
TX_CLK | O | 1 | MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock. Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb SNI mode. The MAC should source TX_EN and TXD_0 using this clock. |
TX_EN | I, PD | 2 | MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0]. RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0]. SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0. |
TXD_0 TXD_1 TXD_2 TXD_3 |
I S, I, PD |
3 4 5 6 |
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50 MHz reference clock. SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI mode). |
RX_CLK | O | 38 | MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode. Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode. |
RX_DV | S, O, PD | 39 | MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0]. Mll mode by default with internal pulldown. RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid indication independent of Carrier Sense. This pin is not used in SNI mode. |
RX_ER | S, O, PU | 41 | MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode. RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s mode. This pin is not required to be used by a MAC in either MII or RMII mode, since the Phy is required to corrupt data on a receive error. This pin is not used in SNI mode. |
RXD_0 RXD_1 RXD_2 RXD_3 |
S, O, PD | 43 44 45 46 |
MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted. RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz. SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode. |
CRS/CRS_DV | S, O, PU | 40 | MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification. SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to frame valid receive data on the RXD_0 signal. |
COL | S, O, PU | 42 | MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes. While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test). In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation. RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision. SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s SNI mode. |
SIGNAL NAME | TYPE | PIN # | DESCRIPTION |
---|---|---|---|
X1 | I | 34 | CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848C/I/VYB/YB and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The DP83848C/I/VYB/YB supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source. |
X2 | O | 33 | CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used. |
CLK_OUT | O | 25 | 25 MHz CLOCK OUTPUT:
In MII mode, this pin provides a 25 MHz clock output to the system. In RMII mode, this pin provides a 50 MHz clock output to the system. This allows other devices to use the reference clock from the DP83848VYB without requiring additional clock sources. |
See Table 6-2 for LED Mode Selection.
SIGNAL NAME | TYPE | PIN # | DESCRIPTION |
---|---|---|---|
LED_LINK | S, O, PU | 28 | LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good. LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active. |
LED_SPEED | S, O, PU | 27 | SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in 10 Mb/s. Functionality of this LED is independent of mode selected. |
LED_ACT/COL | S, O, PU | 26 | ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or Receive. COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be programmed to indicate Full-duplex status instead of Collision. |
SIGNAL NAME | TYPE | PIN #(1) | DESCRIPTION |
---|---|---|---|
TCK | I, PU | 8 | TEST CLOCK |
This pin has a weak internal pullup. | |||
TDI | I, PU | 12 | TEST DATA INPUT |
This pin has a weak internal pullup. | |||
TDO | O | 9 | TEST OUTPUT |
TMS | I, PU | 10 | TEST MODE SELECT |
This pin has a weak internal pullup. | |||
TRST# | I, PU | 11 | TEST RESET: Active low asynchronous test reset. |
This pin has a weak internal pullup. |
SIGNAL NAME | TYPE | PIN # | DESCRIPTION |
---|---|---|---|
RESET_N | I, PU | 29 | RESET: Active Low input that initializes or re-initializes the DP83848VYB. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Section 6.6 section. All strap options are re-initialized as well. |
PWR_DOWN/INT | I, PU | 7 | See Section 7.2.1.3.1 for detailed description. |
The default function of this pin is POWER DOWN. | |||
POWER DOWN: The pin is an active low input in this mode and should be asserted low to put the device in a Power Down mode. | |||
INTERRUPT: The pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs. Although the pin has a weak internal pullup, some applications may require an external pullup resister. Register access is required for the pin to be used as an interrupt mechanism. See Section 7.2.1.3.1.2 for more details on the interrupt mechanisms. |
The DP83848VYB uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pulldown or pullup to change the default strap option. If the default option is required, then there is no need for external pullup or pulldown resistors. Since these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.
SIGNAL NAME | TYPE | PIN # | DESCRIPTION | |||
---|---|---|---|---|---|---|
PHYAD0 (COL) PHYAD1 (RXD1_0) PHYAD2 (RXD0_1) PHYAD3 (RXD1_2) PHYAD4 (RXD1_3) |
S, O, PU S, O, PD |
42 43 44 45 46 |
PHY ADDRESS [4:0]: The DP83848VYB provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset. The DP83848VYB supports PHY Address strapping values 0 (<00000>) through 31 (<11111>).A PHY Adress of 0 puts the part into the Mll isolate Mode. The Mll isolate mode must be selected by strapping Phy Address 0; changing to Address 0 by register write will not put the Phy in the Mll isolate mode. Please refer to Section 6.4.5 for additional information. PHYAD0 pin has weak internal pullup resistor. PHYAD[4:1] pins have weak internal pulldown resistors. |
|||
AN_EN(LED_ACT/COL) AN_1 (LED_SPEED) AN_0 (LED_LINK) |
S, O, PU | 26 27 28 |
Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins. AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83848VYB according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2 kΩ resistors. These pins should NEVER be connected directly to GND or VCC. The value set at this input is latched into the DP83848VYB at Hardware-Reset. The float/pulldown status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default is 111 since the these pin have internal pullups. |
|||
AN_EN | AN1 | AN0 | Forced Mode | |||
0 | 0 | 0 | 10BASE-T, Half-Duplex | |||
0 | 0 | 1 | 10BASE-T, Full-Duplex | |||
0 | 1 | 0 | 100BASE-TX, Half-Duplex | |||
0 | 1 | 1 | 100BASE-TX, Full-Duplex | |||
AN_EN | AN1 | AN0 | Advertised Mode | |||
1 | 0 | 0 | 10BASE-T, Half/Full-Duplex | |||
1 | 0 | 1 | 100BASE-TX, Half/Full-Duplex | |||
1 | 1 | 0 | 10BASE-T, Half-Duplex, 100BASE-TX, Half-Duplex |
|||
1 | 1 | 1 | 10BASE-T, Half/Full-Duplex, 100BASE-TX, Half/Full-Duplex |
|||
MII_MODE (RX_DV) SNI_MODE (TXD_3) |
S, O, PD | 39 6 |
MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default operation (No pullups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII or SNI modes of operation, determined by the status of the SNI_MODE strap. Since the pins include internal pulldowns, the default values are 0. The following table details the configurations: |
|||
MII_MODE | SNI_MODE | MAC Interface Mode | ||||
0 | X | MII Mode | ||||
1 | 0 | RMII Mode | ||||
1 | 1 | 10 Mb SNI Mode | ||||
LED_CFG (CRS) | S, O, PU | 40 | LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled through the strap option. All modes are configurable through register access. See Table 6-2 for LED Mode Selection. |
|||
MDIX_EN (RX_ER) | S, O, PU | 41 | MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pulldown will disable Auto-MDIX mode. |
SIGNAL NAME | TYPE | PIN # | DESCRIPTION |
---|---|---|---|
TD-, TD+ | I/O | 16 17 |
Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. IIn Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3-V bias for operation. |
RD-, RD+ | I/O | 13 14 |
Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling. In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require 3.3-V bias for operation. |
SIGNAL NAME | TYPE | PIN # | DESCRIPTION |
---|---|---|---|
RBIAS | I | 24 | Bias Resistor Connection: A 4.87 kΩ 1% resistor should be connected from RBIAS to GND. |
PFBOUT | O | 23 | Power Feedback Output: Parallel caps, 10 µF (Tantalum preferred) and 0.1 µF, should be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See Section 7.2.1.3 for proper placement pin. |
PFBIN1 PFBIN2 |
I | 18 37 |
Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor of 0.1 µF should be connected close to each pin.(1) |
RESERVED | I/O | 20, 21 | RESERVED: These pins must be pulled-up through 2.2 kΩ resistors to AVDD33 supply. |
SIGNAL NAME | PIN # | DESCRIPTION |
---|---|---|
IOVDD33 | 32, 38 | I/O 3.3-V Supply |
IOGND | 35, 47 | I/O Ground |
DGND | 36 | Digital Ground |
AVDD33 | 22 | Analog 3.3-V Supply |
AGND | 15, 19 | Analog Ground |
GNDPAD | 49 | Ground PAD |
MIN | MAX | UNIT | |
---|---|---|---|
Supply Voltage (VCC) | –0.5 | 4.2 | V |
DC Input Voltage (VIN) | –0.5 | VCC + 0.5 | V |
DC Output Voltage (VOUT) | –0.5 | VCC + 0.5 | V |
Maximum Die Temperature | 121.5 | °C | |
Lead Temperature (TL) (Soldering, 10 sec.) | 260 | °C | |
Storage Temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±4000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1000 |
MIN | MAX | UNIT | |
---|---|---|---|
Supply voltage (VCC) | 3.3 V ± 0.3 | V | |
Commercial | 0 | 70 | °C |
Industrial | –40 | 85 | |
Extended | –40 | 105 | |
Extreme | –40 | 125 | |
Power Dissipation (PD) | 267 | mW |
THERMAL METRIC(1) | DP83848C/I | DP83848VYB/YB | UNIT | |
---|---|---|---|---|
PT [HLQFP] | PTB [LQFP] | |||
48 PINS | 48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 73.9 | 40.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 30.9 | 25.5 | |
RθJB | Junction-to-board thermal resistance | 37.2 | 21 | |
ψJT | Junction-to-top characterization parameter | 2.8 | 2.7 | |
ψJB | Junction-to-board characterization parameter | 37 | 20.9 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | 3.6 |
PARAMETER | TEST CONDITIONS | PIN TYPES |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VIH | Input High Voltage | Nominal VCC | I, | 2.0 | V | ||
I/O | |||||||
VIL | Input Low Voltage | I, | 0.8 | V | |||
I/O | |||||||
IIH | Input High Current | VIN = VCC | I, | 10 | µA | ||
I/O | |||||||
IIL | Input Low Current | VIN = GND | I, | 10 | µA | ||
I/O | |||||||
VOL | Output Low | IOL = 4 mA | O, | 0.4 | V | ||
Voltage | I/O | ||||||
VOH | Output High | IOH = –4 mA | O, | VCC - 0.5 | V | ||
Voltage | I/O | ||||||
IOZ | TRI-STATE | VOUT = VCC | I/O, | ±10 | µA | ||
Leakage | VOUT = GND | O | |||||
VTPTD_100 | 100M Transmit Voltage | PMD Output Pair | 0.95 | 1 | 1.05 | V | |
VTPTDsym | 100M Transmit Voltage Symmetry | PMD Output Pair | ±2% | ||||
VTPTD_10 | 10M Transmit Voltage | PMD Output Pair | 2.2 | 2.5 | 2.8 | V | |
CIN1 | CMOS Input | I | 5 | pF | |||
Capacitance | |||||||
COUT1 | CMOS Output | O | 5 | pF | |||
Capacitance | |||||||
SDTHon | 100BASE-TX | PMD Input Pair | 1000 | mV diff pk-pk | |||
Signal detect turnon threshold | |||||||
SDTHoff | 100BASE-TX | PMD Input Pair | 200 | mV diff pk-pk | |||
Signal detect turnoff threshold | |||||||
VTH1 | 10BASE-T Receive Threshold | PMD Input Pair | 585 | mV | |||
Idd100 | 100BASE-TX | Supply | 81 | mA | |||
(Full Duplex) | |||||||
Idd10 | 100BASE-TX | Supply | 92 | mA | |||
(Full Duplex) | |||||||
Idd | Power Down Mode | CLK2MAC disabled | Supply | 14 | mA |
PARAMETER | DESCRIPTION | NOTES | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
POWER-UP TIMING | ||||||
T2.1.1 | Post Power-Up Stabilization time prior to MDC preamble for register accesses(1) | MDIO is pulled high for 32-bit serial management initialization | 167 | ms | ||
X1 Clock must be stable for a min. of 167 ms at power up. | ||||||
T2.1.2 | Hardware Configuration Latch-in Time from power up(1) | Hardware Configuration Pins are described in the Section 4 section. | 167 | ms | ||
X1 Clock must be stable for a min. of 167 ms at power up. | ||||||
T2.1.3 | Hardware Configuration pins transition to output drivers | 50 | ns | |||
RESET TIMING | ||||||
T2.2.1 | Post RESET Stabilization time prior to MDC preamble for register accesses(2) | MDIO is pulled high for 32-bit serial management initialization | 3 | µs | ||
T2.2.2 | Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard)(2) | Hardware Configuration Pins are described in the Section 4 section | 3 | µs | ||
T2.2.3 | Hardware Configuration pins transition to output drivers | 50 | ns | |||
T2.2.4 | RESET pulse width | X1 Clock must be stable for at min. of 1us during RESET pulse low time. | 1 | µs | ||
MII SERIAL MANAGEMENT TIMING | ||||||
T2.3.1 | MDC to MDIO (Output) Delay Time | 0 | 30 | ns | ||
T2.3.2 | MDIO (Input) to MDC Setup Time | 10 | ns | |||
T2.3.3 | MDIO (Input) to MDC Hold Time | 10 | ns | |||
T2.3.4 | MDC Frequency | 2.5 | 25 | MHz | ||
100 Mb/s MII TRANSMIT TIMING | ||||||
T2.4.1 | TX_CLK High/Low Time | 100 Mb/s Normal mode | 16 | 20 | 24 | ns |
T2.4.2 | TXD[3:0], TX_EN Data Setup to TX_CLK | 100 Mb/s Normal mode | 10 | ns | ||
T2.4.3 | TXD[3:0], TX_EN Data Hold from TX_CLK | 100 Mb/s Normal mode | 0 | ns | ||
100 Mb/s MII RECEIVE TIMING | ||||||
T2.5.1 | RX_CLK High/Low Time(3) | 100 Mb/s Normal mode | 16 | 20 | 24 | ns |
T2.5.2 | RX_CLK to RXD[3:0], RX_DV, RX_ER Delay | 100 Mb/s Normal mode | 10 | 30 | ns | |
100BASE-TX MII TRANSMIT PACKET LATENCY TIMING | ||||||
T2.6.1 | TX_CLK to PMD Output Pair Latency(4) | 100BASE-TX mode | 6 | bits | ||
100BASE-TX TRANSMIT PACKET DEASSERTION TIMING | ||||||
T2.7.1 | TX_CLK to PMD Output Pair Deassertion(5) | 100BASE-TX mode | 5 | bits | ||
100BASE-TX TRANSMIT TIMING (tR/F and Jitter) | ||||||
T2.8.1 | 100 Mb/s PMD Output Pair tR and tF(7) | 3 | 4 | 5 | ns | |
100 Mb/s tR and tF Mismatch(6)(7) | 500 | ps | ||||
T2.8.2 | 100 Mb/s PMD Output Pair Transmit Jitter | 1.4 | ns | |||
100BASE-TX RECEIVE PACKET LATENCY TIMING(10) | ||||||
T2.9.1 | Carrier Sense ON Delay(8) | 100 Mb/s Normal mode(9) | 20 | bits | ||
T2.9.2 | Receive Data Latency | 100 Mb/s Normal mode(9) | 24 | bits | ||
100BASE-TX RECEIVE PACKET DEASSERTION TIMING | ||||||
T2.10.1 | Carrier Sense OFF Delay(11) | 100 Mb/s Normal mode(9) | 24 | bits | ||
10 Mb/s MII TRANSMIT TIMING(12) | ||||||
T2.11.1 | TX_CLK High/Low Time | 10 Mb/s MII mode | 190 | 200 | 210 | ns |
T2.11.2 | TXD[3:0], TX_EN Data Setup to TX_CLK fall | 10 Mb/s MII mode | 25 | ns | ||
T2.11.3 | TXD[3:0], TX_EN Data Hold from TX_CLK rise | 10 Mb/s MII mode | 0 | ns | ||
10 Mb/s MII RECEIVE TIMING | ||||||
T2.12.1 | RX_CLK High/Low Time(13) | 160 | 200 | 240 | ns | |
T2.12.2 | RX_CLK TO RXD[3:0}, RX_DV Delay | 10 Mb/s MII mode | 100 | ns | ||
T2.12.3 | RX_CLK rising edge delay from RXD[3:0], RX_DV Valid | 10 Mb/s MII mode | 100 | ns | ||
10 Mb/s SERIAL MODE (SNI) TRANSMIT TIMING | ||||||
T2.13.1 | TX_CLK High Time | 10 Mb/s Serial mode (SNI) | 20 | 25 | 30 | ns |
T2.13.2 | TX_CLK Low Time | 10 Mb/s Serial mode (SNI) | 70 | 75 | 80 | ns |
T2.13.3 | TXD_0, TX_EN Data Setup to TX_CLK rise | 10 Mb/s Serial mode (SNI) | 25 | ns | ||
T2.13.4 | TXD_0, TX_EN Data Hold from TX_CLK rise | 10 Mb/s Serial mode (SNI) | 0 | ns | ||
10 Mb/s SERIAL MODE (SNI) RECEIVE TIMING | ||||||
T2.14.1 | RX_CLK High/Low Time(14) | 35 | 50 | 65 | ns | |
T2.14.2 | RX_CLK fall to RXD_0, RX_DV Delay | 10 Mb/s Serial mode (SNI) | –10 | 10 | ns | |
10BASE-T TRANSMIT TIMING (START OF PACKET) | ||||||
T2.15.1 | Transmit Output Delay from the | 10 Mb/s MII mode(15) | 3.5 | bits | ||
Falling Edge of TX_CLK | ||||||
T2.15.2 | Transmit Output Delay from the | 10 Mb/s Serial mode (SNI)(15) | 3.5 | bits | ||
Rising Edge of TX_CLK | ||||||
10BASE-T TRANSMIT TIMING (END OF PACKET) | ||||||
T2.16.1 | End of Packet High Time | 250 | 300 | ns | ||
(with '0' ending bit) | ||||||
T2.16.2 | End of Packet High Time | 250 | 300 | ns | ||
(with '1' ending bit) | ||||||
10BASE-T RECEIVE TIMING (START OF PACKET)(17) | ||||||
T2.17.1 | Carrier Sense Turnon Delay (PMD Input Pair to CRS) | 630 | 1000 | ns | ||
T2.17.2 | RX_DV Latency(16) | 10 | bits | |||
T2.17.3 | Receive Data Latency | Measurement shown from SFD | 8 | bits | ||
10BASE-T RECEIVE TIMING (END OF PACKET) | ||||||
T2.18.1 | Carrier Sense Turn Off Delay | 1 | µs | |||
10 Mb/s HEARTBEAT TIMING | ||||||
T2.19.1 | CD Heartbeat Delay | 10 Mb/s half-duplex mode | 1200 | ns | ||
T2.19.2 | CD Heartbeat Duration | 10 Mb/s half-duplex mode | 1000 | ns | ||
10 Mb/s JABBER TIMING | ||||||
T2.20.1 | Jabber Activation Time | 85 | ms | |||
T2.20.2 | Jabber Deactivation Time | 500 | ms | |||
10BASE-T NORMAL LINK PULSE TIMING(18) | ||||||
T2.21.1 | Pulse Width | 100 | ns | |||
T2.21.2 | Pulse Period | 16 | ms | |||
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING(18) | ||||||
T2.22.1 | Clock, Data Pulse Width | 100 | ns | |||
T2.22.2 | Clock Pulse to Clock Pulse | 125 | µs | |||
Period | ||||||
T2.22.3 | Clock Pulse to Data Pulse | Data = 1 | 62 | µs | ||
Period | ||||||
T2.22.4 | Burst Width | 2 | ms | |||
T2.22.5 | FLP Burst to FLP Burst Period | 16 | ms | |||
100BASE-TX SIGNAL DETECT TIMING(19) | ||||||
T2.23.1 | SD Internal Turnon Time | 1 | ms | |||
T2.23.2 | SD Internal Turnoff Time | 350 | µs | |||
100 Mb/s INTERNAL LOOPBACK TIMING | ||||||
T2.24.1 | TX_EN to RX_DV Loopback(21) | 100 Mb/s internal loopback mode(20) | 240 | ns | ||
10 Mb/s INTERNAL LOOPBACK TIMING | ||||||
T2.25.1 | TX_EN to RX_DV Loopback(21) | 10 Mb/s internal loopback mode | 2 | µs | ||
RMII TRANSMIT TIMING | ||||||
T2.26.1 | X1 Clock Period | 50 MHz Reference Clock | 20 | ns | ||
T2.26.2 | TXD[1:0], TX_EN, Data Setup to X1 rising | 4 | ns | |||
T2.26.3 | TXD[1:0], TX_EN, Data Hold from X1 rising | 2 | ns | |||
T2.26.4 | X1 Clock to PMD Output Pair Latency | From X1 Rising edge to first bit of symbol | 17 | bits | ||
RMII RECEIVE TIMING | ||||||
T2.27.1 | X1 Clock Period | 50 MHz Reference Clock | 20 | ns | ||
T2.27.2 | RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising(22)(23)(24) | 2 | 14 | ns | ||
T2.27.3 | CRS ON delay (100Mb) | From JK symbol on PMD Receive Pair to initial assertion of CRS_DV | 18.5 | bits | ||
T2.27.4 | CRS OFF delay (100Mb) | From TR symbol on PMD Receive Pair to initial deassertion of CRS_DV | 27 | bits | ||
T2.27.5 | RXD[1:0] and RX_ER latency (100Mb) | From symbol on Receive Pair. Elasticity buffer set to default value (01) | 38 | bits | ||
ISOLATION TIMING | ||||||
T2.28.1 | From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal mode | 100 | µs | |||
T2.28.2 | From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode | 500 | µs | |||
25 MHz_OUT TIMING | ||||||
T2.29.1 | 25 MHz_OUT High/Low Time(25) | MII mode | 20 | ns | ||
RMII mode | 10 | ns | ||||
T2.29.2 | 25 MHz_OUT propagation delay(25) | Relative to X1 | 8 | ns | ||
100 Mb/s X1 TO TX_CLK TIMING | ||||||
T2.30.1 | X1 to TX_CLK delay(26) | 100 Mb/s Normal mode | 0 | 5 | ns |