The number of applications requiring Ethernet Connectivity continues to expand. Along with this increased market demand is a change in application requirements. Where single channel Ethernet used to be sufficient, many applications such as wireless remote base stations and industrial networking now require DUAL Port functionality for redundancy or system management.
The DP83849I is a highly reliable, feature rich device perfectly suited for industrial applications enabling Ethernet on the factory floor. The DP83849I features two fully independent 10/100 ports for multi-port applications. The unique port switching capability also allows the two ports to be configured to provide fully integrated range extension, media conversion, hardware based failover and port monitoring.
The DP83849I provides optimum flexibility in MPU selection by supporting both MII and RMII interfaces. In addition this device includes a powerful new diagnostics tool to ensure initial network operation and maintenance.
In addition to the TDR scheme, commonly used for detecting faults during installation, the innovative cable diagnostics provides for real time continuous monitoring of the link quality. This allows the system designer to implement a fault prediction mechanism to detect and warn of changing or deteriorating link conditions.
The DP83849I continues to build on its Ethernet expertise and leadership position by providing a powerful combination of features and flexibility, easing Ethernet implementation for the system designer.
PART NUMBER | PACKAGE | BODY SIZE |
---|---|---|
DP83849I | TQFP (80) | 12.00 mm × 12.00 mm |
Changes from E Revision (May 2008) to F Revision
The DP83849I pins are classified into the following interface categories (each interface is described in the sections that follow):
NOTE
Strapping pin option. See Section 3.2.7 for strap definitions.
All DP83849I signal pins are I/O cells regardless of the particular use. The following definitions define the functionality of the I/O cells for each pin.
Type: I | Input |
Type: O | Output |
Type: I/O | Input/Output |
Type OD | Open Drain |
Type: PD, PU | Internal Pulldown/Pullup |
Type: S | Strapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap value is to be changed then an external 2.2-kΩ resistor must be used. See Section 3.2.7 for details.) |
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PIN NO. | NAME | PIN NO. | NAME | |
---|---|---|---|---|
1 | CRS_A/CRS_DV_A/LED_CFG_A | 41 | LED_ACT/LED_COL/AN_EN_B | |
2 | RX_ER_A/MDIX_EN_A | 42 | LED_SPEED_B/AN1_B | |
3 | COL_A | 43 | LED_LINK_B/AN0_B | |
4 | RXD0_A/PHYAD1 | 44 | PWRDOWN_INT_B | |
5 | RXD1_A/PHYAD2 | 45 | TXD3_B/SNI_MODE_B | |
6 | COREGND1 | 46 | TXD2_B | |
7 | PFBIN1 | 47 | TXD1_B | |
8 | RXD2_A/CLK2MAC_DIS | 48 | TXD0_B | |
9 | RXD3_A/ED_EN_A | 49 | TX_EN_B | |
10 | IOGND1 | 50 | TX_CLK_B | |
11 | IOVDD1 | 51 | IOVDD2 | |
12 | TX_CLK_A | 52 | IOGND2 | |
13 | TX_EN_A | 53 | RXD3_B/ED_EN_B | |
14 | TXD0_A | 54 | PFBIN4 | |
15 | TXD1_A | 55 | COREGND2 | |
16 | TXD2_A | 56 | RXD2_B/EXTENDER_EN | |
17 | TXD3_A/SNI_MODE_A | 57 | RXD1_B/PHYAD4 | |
18 | PWRDOWN_INT_A | 58 | RXD0_B/PHYAD3 | |
19 | LED_LINK_A/AN0_A | 59 | COL_B | |
20 | LED_SPEED_A/AN1_A | 60 | RX_ER_B/MDIX_EN_B | |
21 | LED_ACT/LED_COL/AN_EN_A | 61 | CRS_B/CRS_DV_B/LED_CFG_B | |
22 | ANAGND1 | 62 | RX_DV_B/MII_MODE_B | |
23 | TPRDM_A | 63 | RX_CLK_B | |
24 | TPRDP_A | 64 | IOGND3 | |
25 | CDGND1 | 65 | IOVDD3 | |
26 | TPTDM_A | 66 | MDIO | |
27 | TPTDP_A | 67 | MDC | |
28 | PFBIN2 | 68 | CLK2MAC | |
29 | ANAGND2 | 69 | X2 | |
30 | ANA33VDD | 70 | X1 | |
31 | PFBOUT | 71 | RESET_N | |
32 | RBIAS | 72 | TCK | |
33 | ANAGND3 | 73 | TDO | |
34 | PFBIN3 | 74 | TMS | |
35 | TPTDP_B | 75 | TRSTN | |
36 | TPTDM_B | 76 | TDI | |
37 | CDGND2 | 77 | IOGND4 | |
38 | TPRDP_B | 78 | IOVDD4 | |
39 | TPRDM_B | 79 | RX_CLK_A | |
40 | ANAGND4 | 80 | RX_DV_A/MII_MODE_A |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
MDC | I | 67 | MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. |
MDIO | I/O | 66 | MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5-kΩ pullup resistor. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
X1 | I | 70 | CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83849I and must be connected to a 25 MHz 0.005% (+50 ppm) clock source. The DP83849I supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. |
RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50-MHz | |||
0.005% (+50 ppm) CMOS-level oscillator source. | |||
X2 | O | 69 | CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used. |
CLK2MAC | O | 68 | CLOCK TO MAC: |
In MII mode, this pin provides a 25-MHz clock output to the system. | |||
In RMII mode, this pin provides a 50-MHz clock output to the system. | |||
This allows other devices to use the reference clock from the DP83849I without requiring additional clock sources. | |||
If the system does not require the CLK2MAC signal, the CLK2MAC output must be disabled through the CLK2MAC disable strap. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
TX_CLK_A | O | 12 | MII TRANSMIT CLOCK: 25-MHz Transmit clock output in 100-Mb/s mode or 2.5 MHz in 10-Mb/s mode derived from the 25-MHz reference clock. |
TX_CLK_B | 50 | ||
Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive. | |||
SNI TRANSMIT CLOCK: 10-MHz Transmit clock output in 10-Mb/s SNI mode. The MAC must source TX_EN and TXD_0 using this clock. | |||
TX_EN_A | I | 13 | MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0]. |
TX_EN_B | 49 | ||
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0]. | |||
SNI TRANSMIT ENABLE: 10-MHz Transmit clock output in 10-Mb/s SNI mode. The MAC must source TX_EN and TXD_0 using this clock. | |||
TXD[3:0]_A | I | 17, 16, 15, 14 | MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). |
TXD[3:0]_B | 45, 46, 47, 48 | ||
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50-MHz reference clock. | |||
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI mode). | |||
RX_CLK_A | O | 79 | MII RECEIVE CLOCK: Provides the 25-MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode. |
RX_CLK_B | 63 | Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive. | |
SNI RECEIVE CLOCK: Provides the 10-MHz recovered receive clocks for 10 Mb/s SNI mode. | |||
RX_DV_A | O | 80 | MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0]. |
RX_DV_B | 62 | RMII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[1:0]. This signal is not required in RMII mode, because CRS_DV includes the RX_DV signal, but is provided to allow simpler recovery of the Receive data. | |
This pin is not used in SNI mode. | |||
RX_ER_A | O | 2 | MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode. |
RX_ER_B | 60 | RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s mode. This pin is also asserted on detection of a False Carrier event. This pin is not required to be used by a MAC in RMII mode, because the Phy is required to corrupt data on a receive error. | |
This pin is not used in SNI mode. | |||
RXD[3:0]_A | O | 9, 8, 5, 4 | MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted. |
RXD[3:0]_B | 53, 56, 57, 58 | RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz. | |
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode. | |||
CRS_A/CRS_DV_A | O | 1 | MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. |
CRS_B/CRS_DV_B | 61 | RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see Section 4.6. | |
SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to frame valid receive data on the RXD_0 signal. | |||
COL_A | O | 3 | MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes. |
COL_B | 59 | While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test). | |
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation. | |||
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision. | |||
SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s SNI mode. |
The DP83849I supports three configurable LED pins. The LEDs support two operational modes that are selected by the LED mode strap and a third operational mode that is register configurable. The definitions for the LEDs for each mode are detailed in the following table. Because the LEDs are also used as strap options, the polarity of the LED output is dependent on whether the pin is pulled up or down.
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SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
LED_LINK_A | I/O | 19 | LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good. |
LED_LINK_B | 43 | ||
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active. | |||
LED_SPEED_A | I/O | 20 | SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in 10 Mb/s. Functionality of this LED is independent of mode selected. |
LED_SPEED_B | 42 | ||
LED_ACT/LED_COL_A | I/O | 21 | ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or Receive. |
LED_ACT/LED_COL_B | 41 | ||
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be programmed to indicate Full-duplex status instead of Collision. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
TCK | I, PU | 72 | TEST CLOCK: This pin has a weak internal pullup. |
TDO | O | 73 | TEST OUTPUT: |
TMS | I, PU | 74 | TEST MODE SELECT: This pin has a weak internal pullup. |
TRSTN | I, PU | 75 | TEST RESET Active low test reset. This pin has a weak internal pullup. |
TDI | I, PU | 76 | TEST DATA INPUT: This pin has a weak internal pullup. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
RESET_N | I, PU | 71 | RESET: Active Low input that initializes or re-initializes the DP83849I. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Register Block section. All strap options are re-initialized as well. |
PWRDOWN_INT_A | I, PU | 18 | The default function of this pin is POWER DOWN. |
PWRDOWN_INT_B | 44 | ||
POWER DOWN: The pin is an active low input in this mode and must be asserted low to put the device in a Power Down mode. | |||
INTERRUPT: The pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs. Although the pin has a weak internal pullup, some applications may require an external pullup resister. Register access is required for the pin to be used as an interrupt mechanism. See Section 6.2.4.2 for more details on the interrupt mechanisms. |
The DP83849I uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.
A 2.2-kΩ resistor must be used for pulldown or pullup to change the default strap option. If the default option is required, then there is no need for external pullup or pull down resistors. Because these pins may have alternate functions after reset is deasserted, they must not be connected directly to VCC or GND.
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SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION | |||||
---|---|---|---|---|---|---|---|---|
PHYAD1 (RXD0_A) | S, O, PD | 4 | PHY ADDRESS [4:1]: The DP83849I provides four PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset. Phy Address[0] selects between ports A and B. | |||||
PHYAD2 (RXD1_A) | 5 | |||||||
PHYAD3 (RXD0_B) | 58 | The DP83849I supports PHY Address strapping for Port A even values 0 (<0000_0>) through 30 (<1111_0>). Port B will be strapped to odd values 1 (<0000_1>) through 31 (<1111_1>). |
||||||
PHYAD4 (RXD1_B) | 57 | |||||||
PHYAD[4:1] pins have weak internal pulldown resistors. | ||||||||
AN_EN |
S, O, PU | 21 | Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins. AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83849I according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2-kΩ resistors. These pins must NEVER be connected directly to GND or VCC. The value set at this input is latched into the DP83849I at Hardware-Reset. The float/pulldown status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default is 111 because these pins have internal pullups. |
|||||
AN1_A (LED_SPEED_A) | 20 | |||||||
AN0_A (LED_LINK_A) | 19 | |||||||
AN_EN (LED_ACT/LED_COL_B) |
41 | |||||||
AN1_B (LED_SPEED_B) | 42 | |||||||
AN0_B (LED_LINK_B) | 43 | |||||||
AN_EN | AN1 | AN0 | Forced Mode | |||||
0 | 0 | 0 | 10BASE-T, Half-Duplex | |||||
0 | 0 | 1 | 10BASE-T, Full-Duplex | |||||
0 | 1 | 0 | 100BASE-TX, Half-Duplex | |||||
0 | 1 | 1 | 100BASE-TX Full-Duplex | |||||
AN_EN | AN1 | AN0 | Advertised Mode | |||||
1 | 0 | 0 | 10BASE-T, Half/Full-Duplex | |||||
1 | 0 | 1 | 100BASE-TX, Half/Full-Duplex | |||||
1 | 1 | 0 | 10BASE-T, Half-Duplex 100BASE-TX, Half-Duplex |
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1 | 1 | 1 | 10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex |
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MII_MODE_A (RX_DV_A) | S, O, PD | 80 | MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default operation (No pullups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII or SNI modes of operation, determined by the status of the SNI_MODE strap. Because the pins include internal pulldowns, the default values are 0. Both MAC Data Interfaces must have their RMII Mode settings the same; that is, both in RMII mode or both not in RMII mode The following table details the configurations: |
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SNI_MODE_A (TXD3_A) | 17 | |||||||
MII_MODE_B (RX_DV_B) | 62 | |||||||
SNI_MODE_B (TXD3_B) | 45 | |||||||
MII_MODE | SNI_MODE | MAC Interface Mode | ||||||
0 | X | MII Mode | ||||||
1 | 0 | RMII Mode | ||||||
1 | 1 | 10-Mb/s SNI mode | ||||||
LED_CFG_A (CRS_A/CRS_DV_A) |
S, O, PU | 1 | LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled through the strap option. All modes are configurable through register access. See Table 5-2 for LED Mode Selection. |
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LED_CFG_B (CRS_B/CRS_DV_B) |
61 | |||||||
MDIX_EN_A (RX_ER_A) | S, O, PU | 2 | MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pulldown will disable AutoMDIX mode. | |||||
MDIX_EN_B (RX_ER_B) | 60 | |||||||
ED_EN_A (RXD3_A) | S, O, PD | 9 | Energy Detect ENABLE: Default is to disable Energy Detect mode. This strapping option enables Energy Detect mode for the port. In Energy Detect mode, the device will initially be in a low-power state until detecting activity on the wire. An external pullup will enable Energy Detect mode. | |||||
ED_EN_B (RXD3_B) | 53 | |||||||
CLK2MAC_DIS (RXD2_A) | S, O, PD | 8 | Clock to MAC Disable: This strapping option disables (floats) the CLK2MAC pin. Default is to enable CLK2MAC output. An external pullup will disable (float) the CLK2MAC pin. If the system does not require the CLK2MAC signal, the CLK2MAC output must be disabled through this strap option. | |||||
EXTENDER_EN (RXD2_B) | S, O, PD | 56 | Extender Mode Enable: This strapping option enables Extender Mode for both ports. When enabled, the strap will enable Single Clock MII TX and RX modes unless RMII Mode is also strapped. SNI Mode cannot be strapped if Extender Mode is strapped. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
TPTDM_A | I/O | 26 | 10BASE-T or 100BASE-TX Transmit Data
In 10BASE-T or 100BASE-TX: Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3-V bias for operation. |
TPTDP_A | 27 | ||
TPTDM_B | 36 | ||
TPTDP_B | 35 | ||
TPRDM_A | I/O | 23 | 10BASE-T or 100BASE-TX Receive Data
In 10BASE-T or 100BASE-TX: Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling. In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require 3.3-V bias for operation. |
TPRDP_A | 24 | ||
TPRDM_B | 39 | ||
TPRDP_B | 38 |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
RBIAS | I | 32 | Bias Resistor Connection: A 4-87 kΩ 1% resistor must be connected from RBIAS to GND. |
PFBOUT | O | 31 | Power Feedback Output: Parallel caps, 10 µF and 0.1 µF, must be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 13), PFBIN2 (pin 27), PFBIN3 (pin 35), PFBIN4 (pin 49). See Section 6.2.3 for proper placement pin. |
PFBIN1 | I | 7 | Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor of 0.1 µF must be connected close to each pin. Note: Do not supply power to these pins other than from PFBOUT. |
PFBIN2 | 28 | ||
PFBIN3 | 34 | ||
PFBIN4 | 54 |
SIGNAL NAME | PIN NO. | DESCRIPTION |
---|---|---|
IOVDD1, IOVDD2, IOVDD3, IOVDD4 | 11, 51, 65, 78 | I/O 3.3-V Supply |
IOGND1, IOGND2, IOGND3, IOGND4 | 10, 52, 64, 77 | I/O Ground |
COREGND1, COREGND2 | 6, 55 | Core Ground |
CDGND1, CDGND2 | 25, 37 | CD Ground |
ANA33VDD | 30 | Analog 3.3-V Supply |
ANAGND1, ANAGND2, ANAGND3, ANAGND4 | 22, 29, 33, 40 | Analog Ground |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Supply voltage | –0.5 | 4.2 | V |
VIN | DC input voltage | –0.5 | VCC + 0.5 | V |
VOUT | DC output voltage | –0.5 | VCC + 0.5 | V |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(3) | ±4000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage | 3.3 | ±0.3 | V | ||
TA | Industrial Ambient temperature | –40 | 85 | °C | ||
PD | Power dissipation | 594 | mW |
THERMAL METRIC(1) | DP83849I | UNIT | |
---|---|---|---|
TQFP | |||
80 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 57.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 14.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 33.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 32.9 | °C/W |
PARAMETER | TEST CONDITIONS | PIN TYPES | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VIH | Input high voltage | Nominal VCC | I, I/O | 2.0 | V | ||
VIL | Input low voltage | I, I/O | 0.8 | V | |||
IIH | Input high current | VIN = VCC | I, I/O | 10 | µA | ||
IIL | Input low current | VIN = GND | I, I/O | 10 | µA | ||
VOL | Output low voltage | IOL = 4 mA | O, I/O | 0.4 | V | ||
VOH | Output high voltage | IOH = –4 mA | O, I/O | Vcc – 0.5 | V | ||
VledOL | Output low voltage | IOL = 2.5 mA | LED | 0.4 | V | ||
VledOH | Output high voltage | IOH = –2.5 mA | LED | Vcc – 0.5 | V | ||
IOZ | Tri-state leakage | VOUT = VCC | I/O, O | ±10 | µA | ||
VTPTD_100 | 100M Transmit voltage | PMD Output Pair | 0.95 | 1 | 1.05 | V | |
VTPTDsym | 100M Transmit voltage symmetry | PMD Output Pair | ±2% | ||||
VTPTD_10 | 10M Transmit voltage | PMD Output Pair | 2.2 | 2.5 | 2.8 | V | |
CIN1 | CMOS Input capacitance | I | 8 | pF | |||
COUT1 | CMOS Output capacitance | O | 8 | pF | |||
SDTHon | 100BASE-TX Signal detect turnon threshold | PMD Input Pair | 1000 | mV diff pk-pk | |||
SDTHoff | 100BASE-TX Signal detect turnoff threshold | PMD Input Pair | 200 | mV diff pk-pk | |||
VTH1 | 10BASE-T Receive Threshold | PMD Input Pair | 585 | mV | |||
Idd100 | 100BASE-TX (Full Duplex) | Supply | 180 | mA | |||
Idd10 | 10BASE-T (Full Duplex) | Supply | 180 | mA | |||
Idd | Power Down Mode | CLK2MAC disabled | Supply | 9.5 | mA |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER UP TIMING (REFER TO Figure 4-1)(1) | ||||||
T2.1.1 | Post Power Up Stabilization time prior to MDC preamble for register accesses | MDIO is pulled high for 32-bit serial management initialization. X1 Clock must be stable for a minimum of 167 ms at power up. |
167 | ms | ||
T2.1.2 | Hardware Configuration Latch-in Time from power up | Hardware Configuration Pins are described in the Pin Description section. X1 Clock must be stable for a minimum of 167 ms at power up. |
167 | ms | ||
T2.1.3 | Hardware Configuration pins transition to output drivers | 50 | ns | |||
RESET TIMING (REFER TO Figure 4-1)(2) | ||||||
T2.2.1 | Post RESET Stabilization time prior to MDC preamble for register accesses | MDIO is pulled high for 32-bit serial management initialization. | 3 | µs | ||
T2.2.2 | Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard) | Hardware Configuration Pins are described in Pin Description section. | 3 | µs | ||
T2.2.3 | Hardware Configuration pins transition to output drivers | 50 | ns | |||
T2.2.4 | RESET pulse width | X1 Clock must be stable for at minimum of 1 µs during RESET pulse low time. | 1 | µs | ||
MII SERIAL MANAGEMENT TIMING (REFER TO Figure 4-3) | ||||||
T2.3.1 | MDC to MDIO (Output) Delay Time | 0 | 30 | ns | ||
T2.3.2 | MDIO (Input) to MDC Setup Time | 10 | ns | |||
T2.3.3 | MDIO (Input) to MDC Hold Time | 10 | ns | |||
T2.3.4 | MDC Frequency | 2.5 | 25 | MHz | ||
100 Mb/s MII TRANSMIT TIMING (REFER TO Figure 4-4) | ||||||
T2.4.1 | TX_CLK High/Low Time | 100 Mb/s Normal mode | 16 | 20 | 24 | ns |
T2.4.2 | TXD[3:0], TX_EN Data Setup to TX_CLK | 100 Mb/s Normal mode | 10 | ns | ||
T2.4.3 | TXD[3:0], TX_EN Data Hold from TX_CLK | 100 Mb/s Normal mode | 0 | ns | ||
100 Mb/s MII RECEIVE TIMING (REFER TO Figure 4-5)(3) | ||||||
T2.5.1 | RX_CLK High/Low Time | 100 Mb/s Normal mode | 16 | 20 | 24 | ns |
T2.5.2 | RX_CLK to RXD[3:0], RX_DV, RX_ER Delay | 100 Mb/s Normal mode | 10 | 30 | ns | |
100BASE-TX TRANSMIT PACKET LATENCY TIMING (REFER TO Figure 4-6)(4) | ||||||
T2.6.1 | TX_CLK to PMD Output Pair Latency | 100 Mb/s Normal mode | 5 | bits | ||
100BASE-TX TRANSMIT PACKET DEASSERTION TIMING (REFER TO Figure 4-7)(5) | ||||||
T2.7.1 | TX_CLK to PMD Output Pair Deassertion | 100 Mb/s Normal mode | 5 | bits | ||
100BASE-TX TRANSMIT TIMING (tR/F) AND JITTER) (REFER TO Figure 4-8)(6)(7) | ||||||
T2.8.1 | 100 Mb/s PMD Output Pair tR and tF | 3 | 4 | 5 | ns | |
100 Mb/s tR and tF Mismatch | 500 | ps | ||||
T2.8.2 | 100 Mb/s PMD Output Pair Transmit Jitter | 1.4 | ns | |||
100BASE-TX RECEIVE PACKET LATENCY TIMING (REFER TO Figure 4-9)(8)(9) | ||||||
T2.9.1 | Carrier Sense ON Delay | 100 Mb/s Normal mode | 20 | bits | ||
T2.9.2 | Receive Data Latency | 100 Mb/s Normal mode | 24 | bits | ||
100BASE-TX MII RECEIVE PACKET DEASSERTION TIMING (REFER TO Figure 4-10)(9)(10) | ||||||
T2.10.1 | Carrier Sense OFF Delay | 100BASE-TX mode | 24 | bits | ||
10 Mb/s MII TRANSMIT TIMING (REFER TO Figure 4-11)(11) | ||||||
T2.11.1 | TX_CLK High/Low Time | 10 Mb/s MII mode | 190 | 200 | 210 | ns |
T2.11.2 | TXD[3:0], TX_EN Data Setup to TX_CLK fall | 10 Mb/s MII mode | 25 | ns | ||
T2.11.3 | TXD[3:0], TX_EN Data Hold from TX_CLK rise | 10 Mb/s MII mode | 0 | ns | ||
10 Mb/s MII RECEIVE TIMING (REFER TOFigure 4-12)(12) | ||||||
T2.12.1 | RX_CLK High/Low Time | 160 | 200 | 240 | ns | |
T2.12.2 | RX_CLK to RXD[3:0], RX_DV Delay | 10 Mb/s MII mode | 100 | ns | ||
T2.12.3 | RX_CLK rising edge delay from RXD[3:0], RX_DV Valid | 10 Mb/s MII mode | 100 | ns | ||
10 Mb/s SERIAL MODE TRANSMIT TIMING (REFER TO Figure 4-13) | ||||||
T2.13.1 | TX_CLK High Time | 10 Mb/s Serial mode | 20 | 25 | 30 | ns |
T2.13.2 | TX_CLK Low Time | 10 Mb/s Serial mode | 70 | 75 | 80 | ns |
T2.13.3 | TXD_0, TX_EN Data Setup to TX_CLK rise | 10 Mb/s Serial mode | 25 | ns | ||
T2.13.4 | TXD_0, TX_EN Data Hold from TX_CLK rise | 10 Mb/s Serial mode | 0 | ns | ||
10 Mb/s SERIAL MODE RECEIVE TIMING (REFER TO Figure 4-15) (3) | ||||||
T2.14.1 | RTX_CLK high/low Time | 35 | 50 | 65 | ns | |
T2.14.2 | RX_CLK fall to RXD_0, RX_DV Delay | 10 Mb/s Serial mode | –10 | 10 | ns | |
10BASE-T TRANSMIT TIMING (START OF PACKET) (REFER TO Figure 4-16)(13) | ||||||
T2.15.1 | Transmit Output Delay from the Falling Edge of TX_CLK | 10 Mb/s MII mode | 3.5 | bits | ||
T2.15.2 | Transmit Output Delay from the Rising Edge of TX_CLK | 10 Mb/s Serial mode | 3.5 | bits | ||
10BASE-T TRANSMIT TIMING (END OF PACKET) (REFER TO Figure 4-17) | ||||||
T2.16.1 | End of Packet High Time (with 0 ending bit) | 250 | 300 | ns | ||
T2.16.2 | End of Packet High Time (with 1 ending bit) | 250 | 300 | ns | ||
10BASE-T RECEIVE TIMING (START OF PACKET) (REFER TO Figure 4-18)(13)(14) | ||||||
T2.17.1 | Carrier Sense Turnon Delay (PMD Input Pair to CRS) | 630 | 1000 | ns | ||
T2.17.2 | RX_DV Latency | 10 | bits | |||
T2.17.3 | Receive Data Latency | Measurement shown from SFD | 8 | bits | ||
10BASE-T RECEIVE TIMING (END OF PACKET) (REFER TO Figure 4-19) | ||||||
T2.18.1 | Carrier Sense Turn Off Delay | 1.0 | µs | |||
10Mb/s HEARTBEAT TIMING (REFER TO Figure 4-20) | ||||||
T2.19.1 | CD Heartbeat Delay | 10 Mb/s half-duplex mode | 1200 | ns | ||
T2.19.2 | CD Heartbeat Duration | 10 Mb/s half-duplex mode | 1000 | ns | ||
10 Mb/s JABBER TIMING (REFER TO Figure 4-21) | ||||||
T2.20.1 | Jabber Activation Time | 85 | ms | |||
T2.20.2 | Jabber Deactivation Time | 500 | ms | |||
10BASE-T NORMAL LINK PULSE TIMING (REFER TO Figure 4-22)(15) | ||||||
T2.21.1 | Pulse Width | 100 | ns | |||
T2.21.2 | Pulse Period | 16 | ms | |||
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING (REFER TO Figure 4-23)(15) | ||||||
T2.22.1 | Clock, Data Pulse Width | 100 | ns | |||
T2.22.2 | Clock Pulse to Clock Pulse Period | 125 | µs | |||
T2.22.3 | Clock Pulse to Data Pulse Period | Data = 1 | 62 | µs | ||
T2.22.4 | Burst Width | 2 | ms | |||
T2.22.5 | FLP Burst to FLP Burst Period | 16 | ms | |||
100BASE-TX SIGNAL DETECT TIMING (REFER TO )Figure 4-24 | ||||||
T2.23.1 | SD Internal Turnon Time | 1 | ms | |||
T2.23.2 | SD Internal Turnoff Time | 350 | µs | |||
100 Mb/s INTERNAL LOOPBACK TIMING (REFER TO Figure 4-25)(16)(17) | ||||||
T2.24.1 | TX_EN to RX_DV Loopback | 100 Mb/s internal loopback mode | 240 | ns | ||
10 Mb/s INTERNAL LOOPBACK TIMING (REFER TO Figure 4-26)(17) | ||||||
T2.25.1 | TX_EN to RX_DV Loopback | 10 Mb/s internal loopback mode | 2 | µs | ||
RMII TRANSMIT TIMING (REFER TO Figure 4-27) | ||||||
T2.26.1 | X1 Clock Period | 50-MHz Reference Clock | 20 | ns | ||
T2.26.2 | TXD[1:0], TX_EN, Data Setup to X1 rising | 4 | ns | |||
T2.26.3 | TXD[1:0], TX_EN, Data Hold from X1 rising | 2 | ns | |||
T2.26.4 | X1 Clock to PMD Output Pair Latency | 100BASE-TX mode | 11 | bits | ||
RMII RECEIVE TIMING (REFER TO Figure 4-28)(18)(19)(20)(21)(22)(23) | ||||||
T2.27.1 | X1 Clock Period | 50-MHz Reference Clock | 20 | ns | ||
T2.27.2 | RXD[1:0], CRS_DV, RX_DV, and RX_ER output delay from X1 rising | 2 | 14 | ns | ||
T2.27.3 | CRS ON delay (100Mb) | 100BASE-TX mode | 18.5 | bits | ||
T2.27.4 | CRS OFF delay (100Mb) | 100BASE-TX mode | 27 | bits | ||
T2.27.5 | RXD[1:0] and RX_ER latency (100Mb) | 100BASE-TX mode | 38 | bits | ||
SINGLE CLOCK MII (SMII) TRANSMIT TIMING (REFER TO Figure 4-29) | ||||||
T2.28.1 | X1 Clock Period | 25MHz Reference Clock | 40 | ns | ||
T2.28.2 | TXD[3:0], TX_EN Data Setup | To X1 rising | 4 | ns | ||
T2.28.3 | TXD[3:0], TX_EN Data Hold | From X1 rising | 2 | ns | ||
T2.28.4 | X1 Clock to PMD Output Pair Latency (100Mb) | 100BASE-tx MODE | 13 | bits | ||
SINGLE CLOCK MII (SCMII) RECEIVE TIMING (REFER TO Figure 4-30) (25)(26)(27)(28)(29)(30) | ||||||
T2.29.1 | 1 Clock Period | 25MHz Reference Clock | 40 | ns | ||
T2.29.2 | RXD[3:0], RX_DV and RX_ER output delay | From X1 rising | 2 | 18 | ns | |
T2.29.3 | CRS ON delay (100Mb) | 100BASE-TX mode | 19 | bits | ||
T2.29.4 | CRS OFF delay (100Mb) | 100BASE-TX mode | 26 | bits | ||
T2.29.5 | RXD[1:0] and RX_ER latency (100Mb) | 100BASE-TX mode | 56 | bits | ||
ISOLATION TIMING (REFER TO Figure 4-31) | ||||||
T2.30.1 | From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode | 100 | µs | |||
CLK2MAC TIMING (REFER TO Figure 4-32) (31) | ||||||
T2.31.1 | CLK2MAC high/Low Time | MII mode | 20 | ns | ||
RMII mode | 10 | 8 | ns | |||
T2.31.2 | CLK2MAC propagation delay | Relative to X1 | ns | |||
100 Mb/s X1 TO TX_CLK TIMING (REFER TO Figure 4-33) (24) | ||||||
T2.32.1 | X1 to TX_CLK delay | 100 Mb/s Normal mode | 0 | 5 | ns |