SNOSAX1F May   2008  – September 2015 DP83849I

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 System Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 Pin Assignments
    2. 3.2 Signal Descriptions
      1. 3.2.1  Serial Management Interface
      2. 3.2.2  Clock Interface
      3. 3.2.3  MAC Data Interface
      4. 3.2.4  LED Interface
      5. 3.2.5  JTAG Interface
      6. 3.2.6  Reset and Power Down
      7. 3.2.7  Strap Options
      8. 3.2.8  PMD Interface for 10 Mb/s and 100 Mb/s
      9. 3.2.9  Special Connections
      10. 3.2.10 Power Supply Pins
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Specifications
    6. 4.6 AC Timing Requirements
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Auto-Negotiation
        1. 5.3.1.1 Auto-Negotiation Pin Control
        2. 5.3.1.2 Auto-Negotiation Register Control
        3. 5.3.1.3 Auto-Negotiation Parallel Detection
        4. 5.3.1.4 Auto-Negotiation Restart
        5. 5.3.1.5 Auto-Negotiation Complete Time
        6. 5.3.1.6 Enabling Auto-Negotiation Through Software
      2. 5.3.2 Auto-MDIX
      3. 5.3.3 LED Interface
        1. 5.3.3.1 LEDs
        2. 5.3.3.2 LED Direct Control
      4. 5.3.4 Internal Loopback
      5. 5.3.5 BIST
      6. 5.3.6 Energy Detect Mode
      7. 5.3.7 Link Diagnostic Capabilities
        1. 5.3.7.1 Linked Cable Status
        2. 5.3.7.2 Polarity Reversal
          1. 5.3.7.2.1 Cable Swap Indication
          2. 5.3.7.2.2 100 MB Cable Length Estimation
          3. 5.3.7.2.3 Frequency Offset Relative to Link Partner
          4. 5.3.7.2.4 Cable Signal Quality Estimation
          5. 5.3.7.2.5 Link Quality Monitor
        3. 5.3.7.3 Link Quality Monitor Control and Status
          1. 5.3.7.3.1 Checking Current Parameter Values
          2. 5.3.7.3.2 Threshold Control
        4. 5.3.7.4 TDR Cable Diagnostics
          1. 5.3.7.4.1 TDR Pulse Generator
          2. 5.3.7.4.2 TDR Pulse Monitor
          3. 5.3.7.4.3 TDR Control Interface
          4. 5.3.7.4.4 TDR Results
    4. 5.4 Device Functional Modes
      1. 5.4.1 MII Interface
        1. 5.4.1.1 Nibble-wide MII Data Interface
        2. 5.4.1.2 Collision Detect
        3. 5.4.1.3 Carrier Sense
      2. 5.4.2 Reduced MII Interface
      3. 5.4.3 802.3u MII Serial Management Interface
        1. 5.4.3.1 Serial Management Register Access
        2. 5.4.3.2 Serial Management Preamble Suppression
        3. 5.4.3.3 Simultaneous Register Write
      4. 5.4.4 MAC Interface
        1. 5.4.4.1 10-Mb Serial Network Interface (SNI)
        2. 5.4.4.2 Single Clock MII Mode
        3. 5.4.4.3 Flexible MII Port Assignment
          1. 5.4.4.3.1 RX MII Port Mapping
          2. 5.4.4.3.2 TX MII Port Mapping
          3. 5.4.4.3.3 Common Flexible MII Port Configurations
        4. 5.4.4.4 Strapped Extender Mode
        5. 5.4.4.5 Notes and Restrictions
      5. 5.4.5 PHY Address
        1. 5.4.5.1 MII Isolate Mode
      6. 5.4.6 Half Duplex vs Full Duplex
      7. 5.4.7 Reset Operation
        1. 5.4.7.1 Hardware Reset
        2. 5.4.7.2 Full Software Reset
        3. 5.4.7.3 Soft Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
      2. 5.5.2 100BASE-TX Receiver
      3. 5.5.3 Analog Front End
        1. 5.5.3.1  Digital Signal Processor
        2. 5.5.3.2  Digital Adaptive Equalization and Gain Control
        3. 5.5.3.3  Signal Detect
        4. 5.5.3.4  MLT-3 to NRZI Decoder
        5. 5.5.3.5  NRZI to NRZ
        6. 5.5.3.6  Serial to Parallel
        7. 5.5.3.7  Descrambler
        8. 5.5.3.8  Code-Group Alignment
        9. 5.5.3.9  4B/5B Decoder
        10. 5.5.3.10 100BASE-TX Link Integrity Monitor
        11. 5.5.3.11 BAD SSD Detection
      4. 5.5.4 10BASE-T Transceiver Module
        1. 5.5.4.1  Operational Modes
        2. 5.5.4.2  Smart Squelch
        3. 5.5.4.3  Collision Detection and SQE
        4. 5.5.4.4  Carrier Sense
        5. 5.5.4.5  Normal Link Pulse Detection/Generation
        6. 5.5.4.6  Jabber Function
        7. 5.5.4.7  Automatic Link Polarity Detection and Correction
        8. 5.5.4.8  Transmit and Receive Filtering
        9. 5.5.4.9  Transmitter
        10. 5.5.4.10 Receiver
    6. 5.6 Register Block
      1. 5.6.1 Register Definition
        1. 5.6.1.1  Basic Mode Control Register (BMCR)
        2. 5.6.1.2  Basic Mode Status Register (BMSR)
        3. 5.6.1.3  PHY Identifier Register #1 (PHYIDR1)
        4. 5.6.1.4  PHY Identifier Register #2 (PHYIDR2)
        5. 5.6.1.5  Auto-Negotiation Advertisement Register (ANAR)
        6. 5.6.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.6.1.7  Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 5.6.1.8  Auto-Negotiate Expansion Register (ANER)
        9. 5.6.1.9  Auto-Negotiation Next Page Transmit Register (ANNPTR)
        10. 5.6.1.10 PHY Status Register (PHYSTS)
        11. 5.6.1.11 MII Interrupt Control Register (MICR)
        12. 5.6.1.12 MII Interrupt Status and Miscellaneous Control Register (MICR)
        13. 5.6.1.13 Page Select Register (PAGESEL)
      2. 5.6.2 Extended Registers - Page 0
        1. 5.6.2.1  False Carrier Sense Counter Register (FCSCR)
        2. 5.6.2.2  Receiver Error Counter Register (RECR)
        3. 5.6.2.3  100 Mb/s PCS Configuration and Status Register (PCSR)
        4. 5.6.2.4  RMII and Bypass Register (RBR)
        5. 5.6.2.5  LED Direct Control Register (LEDCR)
        6. 5.6.2.6  PHY Control Register (PHYCR)
        7. 5.6.2.7  10BASE-T Status/Control Register (10BTSCR)
        8. 5.6.2.8  CD Test and BIST Extensions Register (CDCTRL1)
        9. 5.6.2.9  Phy Control Register 2 (PHYCR2)
        10. 5.6.2.10 Energy Detect Control (EDCR)
      3. 5.6.3 Link Diagnostics Registers - Page 2
        1. 5.6.3.1  100Mb Length Detect Register (LEN100_DET), Page 2, address 14h
        2. 5.6.3.2  100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h
        3. 5.6.3.3  TDR Control Register (TDR_CTRL), Page 2, address 16h
        4. 5.6.3.4  TDR Window Register (TDR_WIN), Page 2, address 17h
        5. 5.6.3.5  TDR Peak Register (TDR_PEAK), Page 2, address 18h
        6. 5.6.3.6  TDR Threshold Register (TDR_THR), Page 2, address 19h
        7. 5.6.3.7  Variance Control Register (VAR_CTRL), Page 2, address 1Ah
        8. 5.6.3.8  Variance Data Register (VAR_DATA), Page 2, address 1Bh
        9. 5.6.3.9  Link Quality Monitor Register (LQMR), Page 2, address 1Dh
        10. 5.6.3.10 Link Quality Data Register (LQDR), Page 2
  6. 6 Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 TPI Network Circuit
        2. 6.2.2.2 Clock In (X1) Requirements
          1. 6.2.2.2.1 Oscillator
          2. 6.2.2.2.2 Crystal
      3. 6.2.3 Power Feedback Circuit
      4. 6.2.4 Power Down/Interrupt
        1. 6.2.4.1 Power Down Control Mode
        2. 6.2.4.2 Interrupt Mechanisms
      5. 6.2.5 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 PCB Layer Stacking
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Community Resources
      1. 9.1.1 Community Resources
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
VCC Supply voltage –0.5 4.2 V
VIN DC input voltage –0.5 VCC + 0.5 V
VOUT DC output voltage –0.5 VCC + 0.5 V
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All parameters are specified by test, statistical analysis, or design.

4.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(3) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) RZAP = 1.5 kΩ, CZAP = 120 pF

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 3.3 ±0.3 V
TA Industrial Ambient temperature –40 85 °C
PD Power dissipation 594 mW

4.4 Thermal Information

THERMAL METRIC(1) DP83849I UNIT
TQFP
80 PINS
RθJA Junction-to-ambient thermal resistance 57.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.6 °C/W
RθJB Junction-to-board thermal resistance 33.3 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 32.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

4.5 DC Specifications

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS PIN TYPES MIN TYP MAX UNIT
VIH Input high voltage Nominal VCC I, I/O 2.0 V
VIL Input low voltage I, I/O 0.8 V
IIH Input high current VIN = VCC I, I/O 10 µA
IIL Input low current VIN = GND I, I/O 10 µA
VOL Output low voltage IOL = 4 mA O, I/O 0.4 V
VOH Output high voltage IOH = –4 mA O, I/O Vcc – 0.5 V
VledOL Output low voltage IOL = 2.5 mA LED 0.4 V
VledOH Output high voltage IOH = –2.5 mA LED Vcc – 0.5 V
IOZ Tri-state leakage VOUT = VCC I/O, O ±10 µA
VTPTD_100 100M Transmit voltage PMD Output Pair 0.95 1 1.05 V
VTPTDsym 100M Transmit voltage symmetry PMD Output Pair ±2%
VTPTD_10 10M Transmit voltage PMD Output Pair 2.2 2.5 2.8 V
CIN1 CMOS Input capacitance I 8 pF
COUT1 CMOS Output capacitance O 8 pF
SDTHon 100BASE-TX Signal detect turnon threshold PMD Input Pair 1000 mV diff pk-pk
SDTHoff 100BASE-TX Signal detect turnoff threshold PMD Input Pair 200 mV diff pk-pk
VTH1 10BASE-T Receive Threshold PMD Input Pair 585 mV
Idd100 100BASE-TX (Full Duplex) Supply 180 mA
Idd10 10BASE-T (Full Duplex) Supply 180 mA
Idd Power Down Mode CLK2MAC disabled Supply 9.5 mA

4.6 AC Timing Requirements

MIN NOM MAX UNIT
POWER UP TIMING (REFER TO Figure 4-1)(1)
T2.1.1 Post Power Up Stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization.
X1 Clock must be stable for a minimum of 167 ms at power up.		 167 ms
T2.1.2 Hardware Configuration Latch-in Time from power up Hardware Configuration Pins are described in the Pin Description section.
X1 Clock must be stable for a minimum of 167 ms at power up.		 167 ms
T2.1.3 Hardware Configuration pins transition to output drivers 50 ns
RESET TIMING (REFER TO Figure 4-1)(2)
T2.2.1 Post RESET Stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization. 3 µs
T2.2.2 Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard) Hardware Configuration Pins are described in Pin Description section. 3 µs
T2.2.3 Hardware Configuration pins transition to output drivers 50 ns
T2.2.4 RESET pulse width X1 Clock must be stable for at minimum of 1 µs during RESET pulse low time. 1 µs
MII SERIAL MANAGEMENT TIMING (REFER TO Figure 4-3)
T2.3.1 MDC to MDIO (Output) Delay Time 0 30 ns
T2.3.2 MDIO (Input) to MDC Setup Time 10 ns
T2.3.3 MDIO (Input) to MDC Hold Time 10 ns
T2.3.4 MDC Frequency 2.5 25 MHz
100 Mb/s MII TRANSMIT TIMING (REFER TO Figure 4-4)
T2.4.1 TX_CLK High/Low Time 100 Mb/s Normal mode 16 20 24 ns
T2.4.2 TXD[3:0], TX_EN Data Setup to TX_CLK 100 Mb/s Normal mode 10 ns
T2.4.3 TXD[3:0], TX_EN Data Hold from TX_CLK 100 Mb/s Normal mode 0 ns
100 Mb/s MII RECEIVE TIMING (REFER TO Figure 4-5)(3)
T2.5.1 RX_CLK High/Low Time 100 Mb/s Normal mode 16 20 24 ns
T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 30 ns
100BASE-TX TRANSMIT PACKET LATENCY TIMING (REFER TO Figure 4-6)(4)
T2.6.1 TX_CLK to PMD Output Pair Latency 100 Mb/s Normal mode 5 bits
100BASE-TX TRANSMIT PACKET DEASSERTION TIMING (REFER TO Figure 4-7)(5)
T2.7.1 TX_CLK to PMD Output Pair Deassertion 100 Mb/s Normal mode 5 bits
100BASE-TX TRANSMIT TIMING (tR/F) AND JITTER) (REFER TO Figure 4-8)(6)(7)
T2.8.1 100 Mb/s PMD Output Pair tR and tF 3 4 5 ns
100 Mb/s tR and tF Mismatch 500 ps
T2.8.2 100 Mb/s PMD Output Pair Transmit Jitter 1.4 ns
100BASE-TX RECEIVE PACKET LATENCY TIMING (REFER TO Figure 4-9)(8)(9)
T2.9.1 Carrier Sense ON Delay 100 Mb/s Normal mode 20 bits
T2.9.2 Receive Data Latency 100 Mb/s Normal mode 24 bits
100BASE-TX MII RECEIVE PACKET DEASSERTION TIMING (REFER TO Figure 4-10)(9)(10)
T2.10.1 Carrier Sense OFF Delay 100BASE-TX mode 24 bits
10 Mb/s MII TRANSMIT TIMING (REFER TO Figure 4-11)(11)
T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns
T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode 25 ns
T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode 0 ns
10 Mb/s MII RECEIVE TIMING (REFER TOFigure 4-12)(12)
T2.12.1 RX_CLK High/Low Time 160 200 240 ns
T2.12.2 RX_CLK to RXD[3:0], RX_DV Delay 10 Mb/s MII mode 100 ns
T2.12.3 RX_CLK rising edge delay from RXD[3:0], RX_DV Valid 10 Mb/s MII mode 100 ns
10 Mb/s SERIAL MODE TRANSMIT TIMING (REFER TO Figure 4-13)
T2.13.1 TX_CLK High Time 10 Mb/s Serial mode 20 25 30 ns
T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode 70 75 80 ns
T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise 10 Mb/s Serial mode 25 ns
T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 10 Mb/s Serial mode 0 ns
10 Mb/s SERIAL MODE RECEIVE TIMING (REFER TO Figure 4-15) (3)
T2.14.1 RTX_CLK high/low Time 35 50 65 ns
T2.14.2 RX_CLK fall to RXD_0, RX_DV Delay 10 Mb/s Serial mode –10 10 ns
10BASE-T TRANSMIT TIMING (START OF PACKET) (REFER TO Figure 4-16)(13)
T2.15.1 Transmit Output Delay from the Falling Edge of TX_CLK 10 Mb/s MII mode 3.5 bits
T2.15.2 Transmit Output Delay from the Rising Edge of TX_CLK 10 Mb/s Serial mode 3.5 bits
10BASE-T TRANSMIT TIMING (END OF PACKET) (REFER TO Figure 4-17)
T2.16.1 End of Packet High Time (with 0 ending bit) 250 300 ns
T2.16.2 End of Packet High Time (with 1 ending bit) 250 300 ns
10BASE-T RECEIVE TIMING (START OF PACKET) (REFER TO Figure 4-18)(13)(14)
T2.17.1 Carrier Sense Turnon Delay (PMD Input Pair to CRS) 630 1000 ns
T2.17.2 RX_DV Latency 10 bits
T2.17.3 Receive Data Latency Measurement shown from SFD 8 bits
10BASE-T RECEIVE TIMING (END OF PACKET) (REFER TO Figure 4-19)
T2.18.1 Carrier Sense Turn Off Delay 1.0 µs
10Mb/s HEARTBEAT TIMING (REFER TO Figure 4-20)
T2.19.1 CD Heartbeat Delay 10 Mb/s half-duplex mode 1200 ns
T2.19.2 CD Heartbeat Duration 10 Mb/s half-duplex mode 1000 ns
10 Mb/s JABBER TIMING (REFER TO Figure 4-21)
T2.20.1 Jabber Activation Time 85 ms
T2.20.2 Jabber Deactivation Time 500 ms
10BASE-T NORMAL LINK PULSE TIMING (REFER TO Figure 4-22)(15)
T2.21.1 Pulse Width 100 ns
T2.21.2 Pulse Period 16 ms
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING (REFER TO Figure 4-23)(15)
T2.22.1 Clock, Data Pulse Width 100 ns
T2.22.2 Clock Pulse to Clock Pulse Period 125 µs
T2.22.3 Clock Pulse to Data Pulse Period Data = 1 62 µs
T2.22.4 Burst Width 2 ms
T2.22.5 FLP Burst to FLP Burst Period 16 ms
100BASE-TX SIGNAL DETECT TIMING (REFER TO )Figure 4-24
T2.23.1 SD Internal Turnon Time 1 ms
T2.23.2 SD Internal Turnoff Time 350 µs
100 Mb/s INTERNAL LOOPBACK TIMING (REFER TO Figure 4-25)(16)(17)
T2.24.1 TX_EN to RX_DV Loopback 100 Mb/s internal loopback mode 240 ns
10 Mb/s INTERNAL LOOPBACK TIMING (REFER TO Figure 4-26)(17)
T2.25.1 TX_EN to RX_DV Loopback 10 Mb/s internal loopback mode 2 µs
RMII TRANSMIT TIMING (REFER TO Figure 4-27)
T2.26.1 X1 Clock Period 50-MHz Reference Clock 20 ns
T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising 4 ns
T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising 2 ns
T2.26.4 X1 Clock to PMD Output Pair Latency 100BASE-TX mode 11 bits
RMII RECEIVE TIMING (REFER TO Figure 4-28)(18)(19)(20)(21)(22)(23)
T2.27.1 X1 Clock Period 50-MHz Reference Clock 20 ns
T2.27.2 RXD[1:0], CRS_DV, RX_DV, and RX_ER output delay from X1 rising 2 14 ns
T2.27.3 CRS ON delay (100Mb) 100BASE-TX mode 18.5 bits
T2.27.4 CRS OFF delay (100Mb) 100BASE-TX mode 27 bits
T2.27.5 RXD[1:0] and RX_ER latency (100Mb) 100BASE-TX mode 38 bits
SINGLE CLOCK MII (SMII) TRANSMIT TIMING (REFER TO Figure 4-29)
T2.28.1 X1 Clock Period 25MHz Reference Clock 40 ns
T2.28.2 TXD[3:0], TX_EN Data Setup To X1 rising 4 ns
T2.28.3 TXD[3:0], TX_EN Data Hold From X1 rising 2 ns
T2.28.4 X1 Clock to PMD Output Pair Latency (100Mb) 100BASE-tx MODE 13 bits
SINGLE CLOCK MII (SCMII) RECEIVE TIMING (REFER TO Figure 4-30) (25)(26)(27)(28)(29)(30)
T2.29.1 1 Clock Period 25MHz Reference Clock 40 ns
T2.29.2 RXD[3:0], RX_DV and RX_ER output delay From X1 rising 2 18 ns
T2.29.3 CRS ON delay (100Mb) 100BASE-TX mode 19 bits
T2.29.4 CRS OFF delay (100Mb) 100BASE-TX mode 26 bits
T2.29.5 RXD[1:0] and RX_ER latency (100Mb) 100BASE-TX mode 56 bits
ISOLATION TIMING (REFER TO Figure 4-31)
T2.30.1 From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode 100 µs
CLK2MAC TIMING (REFER TO Figure 4-32) (31)
T2.31.1 CLK2MAC high/Low Time MII mode 20 ns
RMII mode 10 8 ns
T2.31.2 CLK2MAC propagation delay Relative to X1 ns
100 Mb/s X1 TO TX_CLK TIMING (REFER TO Figure 4-33) (24)
T2.32.1 X1 to TX_CLK delay 100 Mb/s Normal mode 0 5 ns
(1) In RMII Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84 ms.
(2) It is important to choose pullup and/or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
(3) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.
(4) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
(5) Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
(6) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
(7) Rise and fall times taken at 10% and 90% of the +1 or –1 amplitude.
(8) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(9) 1 bit time = 10 ns in 100 Mb/s mode.
(10) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
(11) An attached Mac must drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge of TX_CLK.
(12) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.
(13) 1 bit time = 100 ns in 10 Mb/s mode.
(14) 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV
(15) These specifications represent transmit timings.
(16) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the initial 550 µs “dead-time”.
(17) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
(18) Per the RMII Specification, output delays assume a 25-pF load.
(19) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion.
(20) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.
(21) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
(22) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial deassertion of CRS_DV.
(23) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set to the default value (01).
(24) X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data.
(25) Latency measurement is made from the X1 Rising edge to the first bit of symbol.
(26) Output delays assume a 25pF load.
(27) CRS is asserted and deasserted asynchronously relative to the reference clock.
(28) CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to assertion of CRS_DV
(29) CRS_OFF delay is measured from the first bit of the TR symbol on the PMD Receive Pair to deassertion of CRS_DV.
(30) Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with the Elasticity Buffer set to the default value (01).
(31) CLK2MAC characteristics are dependent upon the X1 input characteristics.
DP83849I timing_1_snls250.gif Figure 4-1 Power Up Timing
DP83849I timing_2_snls250.gif Figure 4-2 Reset Timing
DP83849I timing_3_snls250.gif Figure 4-3 MII Serial Management Timing
DP83849I timing_4_snls250.gif Figure 4-4 100 Mb/s MII Transmit Timing
DP83849I timing_5_snls250.gif Figure 4-5 100 Mb/s MII Receive Timing
DP83849I timing_6_snls250.gif Figure 4-6 100BASE-TX MII Transmit Packet Latency Timing
DP83849I timing_7_snls250.gif Figure 4-7 100BASE-TX MII Transmit Packet Deassertion Timing
DP83849I timing_8_snls250.gif Figure 4-8 100BASE-TX Transmit Timing (tR/F and Jitter)
DP83849I timing_9_snls250.gif Figure 4-9 100BASE-TX MII Receive Packet Latency Timing
DP83849I timing_10_snls250.gif Figure 4-10 100BASE-TX MII Receive Packet Deassertion Timing
DP83849I timing_11_snls250.gif Figure 4-11 10 Mb/s MII Transmit Timing
DP83849I timing_12_snls250.gif Figure 4-12 10 Mb/s MII Receive Timing
DP83849I timing_13_snls250.gif Figure 4-13 10BASE-T Transmit Timing (Start of Packet)
DP83849I timing_14_snls250.gif Figure 4-14 10BASE-T Transmit Timing (End of Packet)
DP83849I td_01_10mbs_ser_mode_rcve_tmng.gif Figure 4-15 10 Mb/s Serial Mode Receive Timing
DP83849I timing_15_snls250.gif Figure 4-16 10BASE-T Transmit Timing (Start of Packet)
DP83849I timing_14_snls250.gif Figure 4-17 10BASE-T Transmit Timing (End of Packet)
DP83849I timing_15_snls250.gif Figure 4-18 10BASE-T Receive Timing (Start of Packet)
DP83849I timing_16_snls250.gif Figure 4-19 10BASE-T Receive Timing (End of Packet)
DP83849I timing_17_snls250.gif Figure 4-20 10 Mb/s Heartbeat Timing
DP83849I timing_18_snls250.gif Figure 4-21 10 Mb/s Jabber Timing
DP83849I timing_19_snls250.gif Figure 4-22 10BASE-T Normal Link Pulse Timing
DP83849I timing_20_snls250.gif Figure 4-23 Auto-Negotiation Fast Link Pulse (FLP) Timing
DP83849I timing_21_snls250.gif Figure 4-24 100BASE-TX Signal Detect Timing
DP83849I timing_22_snls250.gif Figure 4-25 100 Mb/s Internal Loopback Timing
DP83849I timing_23_snls250.gif Figure 4-26 10 Mb/s Internal Loopback Timing
DP83849I timing_24_snls250.gif Figure 4-27 RMII Transmit Timing
DP83849I timing_25_snls250.gif Figure 4-28 RMII Receive Timing
DP83849I td_02_sngl_clck_mii_trxmt_tmng_snosax1.gif Figure 4-29 Single Clock MII (SCMII) Transmit Timing
DP83849I td_03_sngl_clck_mii_rcve_tmng_snosax1.gif Figure 4-30 Single Clock MII (SCMII) Receive Timing
DP83849I timing_26_snls250.gif Figure 4-31 Isolation Timing
DP83849I td_04_clk2mac_timing_snosax1.gif Figure 4-32 CLK2MAC timing
DP83849I timing_27_snls250.gif Figure 4-33 100 Mb/s X1 to TX_CLK Timing