SNLS484H February 2015 – June 2024 DP83867CR , DP83867IR
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
This register provides receive configuration for Wake-on-LAN (WoL).
BIT | BIT NAME | DEFAULT | DESCRIPTION |
---|---|---|---|
15:12 | RESERVED | 0, RO | RESERVED |
11 | WOL_OUT_CLEAR | 0, RW, SC | Clear Wake-on-LAN Output: This bit is only applicable when configured for level mode. 1 = Clear Wake-on-LAN output |
10:9 | WOL_OUT_STRETCH | 00, RW | Wake-on-LAN Output Stretch: If WoL out is configured for pulse mode, the pulse length is defined as the following number of 125MHz clock cycles: 11 = 64 clock cycles 10 = 32 clock cycles 01 = 16 clock cycles 00 = 8 clock cycles |
8 | WOL_OUT_MODE | 0, RW | Wake-on-LAN Output Mode: 1 = Level Mode. WoL is cleared by a write to WOL_OUT_CLEAR (bit 11). 0 = Pulse Mode. Pulse width is configured via WOL_OUT_STRETCH (bits 10:9). |
7 | ENHANCED_MAC_SUPPORT | 0, RW | Enable Enhanced Receive Features: 1 = Enable for Wake-on-LAN, CRC check, and Receive 1588 indication. 0 = Normal operation. |
6 | RESERVED | 0, RO | RESERVED |
5 | SCRON_EN | 0, RW | Enable SecureOn Password: 1 = SecureOn Password enabled. 0 = SecureOn Password disabled. |
4 | WAKE_ON_UCAST | 0, RW | Wake on Unicast Packet: 1 = Issue an interrupt upon reception of Unicast packet. 0 = Do not issue an interrupt upon reception of Unicast packet. |
3 | RESERVED | 0, RO | RESERVED |
2 | WAKE_ON_BCAST | 1, RW | Wake on Broadcast Packet: 1 = Issue an interrupt upon reception of Broadcast packet. 0 = Do not issue an interrupt upon reception of Broadcast packet. |
1 | WAKE_ON_PATTERN | 0, RW | Wake on Pattern Match: 1 = Issue an interrupt upon pattern match. 0 = Do not issue an interrupt upon pattern match. |
0 | WAKE_ON_MAGIC | 0, RW | Wake on Magic Packet: 1 = Issue an interrupt upon reception of Magic packet. 0 = Do not issue an interrupt upon reception of Magic packet. |