SNLS484H February 2015 – June 2024 DP83867CR , DP83867IR
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
When the DP83867 is operating in 1000Mb master mode, variation of the RX_SFD pulse can be estimated using the Skew FIFO Status register (register address 0x0055) bit[7:4]. The value read from the Skew FIFO Status register bit[7:4] must be multiplied by 8ns to estimate the RX_SFD variation added to the baseline latency.
Example: While operating in master 1000Mb mode, a
value of 0x2 is read from the Skew FIFO register bit[7:4].
2 ×
8ns = 16ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline
latency.