SNLS484H February   2015  – June 2024 DP83867CR , DP83867IR

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1.     7
    2. 5.1 Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Power-Up Timing
    7. 6.7  Reset Timing
    8. 6.8  MII Serial Management Timing
    9. 6.9  RGMII Timing
    10. 6.10 GMII Transmit Timing
    11. 6.11 GMII Receive Timing
    12. 6.12 100Mbps MII Transmit Timing
    13. 6.13 100Mbps MII Receive Timing #GUID-033E0939-17C5-4DC1-9C2C-A3998C85D8B1/SNLS4845065
    14. 6.14 10Mbps MII Transmit Timing
    15. 6.15 10Mbps MII Receive Timing
    16. 6.16 DP83867IR/CR Start of Frame Detection Timing
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 WoL (Wake-on-LAN) Packet Detection
        1. 7.3.1.1 Magic Packet Structure
        2. 7.3.1.2 Magic Packet Example
        3. 7.3.1.3 Wake-on-LAN Configuration and Status
      2. 7.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 7.3.2.1 SFD Latency Variation and Determinism
          1. 7.3.2.1.1 1000Mb SFD Variation in Master Mode
          2. 7.3.2.1.2 1000Mb SFD Variation in Slave Mode
          3. 7.3.2.1.3 100Mb SFD Variation
      3. 7.3.3 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 MAC Interfaces
        1. 7.4.1.1 Reduced GMII (RGMII)
          1. 7.4.1.1.1 1000Mbps Mode Operation
          2. 7.4.1.1.2 1000Mbps Mode Timing
          3. 7.4.1.1.3 10- and 100Mbps Mode
        2. 7.4.1.2 Gigabit MII (GMII)
        3. 7.4.1.3 Media Independent Interface (MII)
          1. 7.4.1.3.1 Nibble-wide MII Data Interface
          2. 7.4.1.3.2 Collision Detect
          3. 7.4.1.3.3 Carrier Sense
      2. 7.4.2 Serial Management Interface
        1. 7.4.2.1 Extended Address Space Access
          1. 7.4.2.1.1 Write Address Operation
          2. 7.4.2.1.2 Read Address Operation
          3. 7.4.2.1.3 Write (No Post Increment) Operation
          4. 7.4.2.1.4 Read (No Post Increment) Operation
          5. 7.4.2.1.5 Write (Post Increment) Operation
          6. 7.4.2.1.6 Read (Post Increment) Operation
          7. 7.4.2.1.7 Example of Read Operation Using Indirect Register Access
          8. 7.4.2.1.8 Example of Write Operation Using Indirect Register Access
      3. 7.4.3 Auto-Negotiation
        1. 7.4.3.1 Speed and Duplex Selection - Priority Resolution
        2. 7.4.3.2 Master and Slave Resolution
        3. 7.4.3.3 Pause and Asymmetrical Pause Resolution
        4. 7.4.3.4 Next Page Support
        5. 7.4.3.5 Parallel Detection
        6. 7.4.3.6 Restart Auto-Negotiation
        7. 7.4.3.7 Enabling Auto-Negotiation Through Software
        8. 7.4.3.8 Auto-Negotiation Complete Time
        9. 7.4.3.9 Auto-MDIX Resolution
      4. 7.4.4 Loopback Mode
        1. 7.4.4.1 Near-End Loopback
          1. 7.4.4.1.1 MII Loopback
          2. 7.4.4.1.2 PCS Loopback
          3. 7.4.4.1.3 Digital Loopback
          4. 7.4.4.1.4 Analog Loopback
        2. 7.4.4.2 External Loopback
        3. 7.4.4.3 Far-End (Reverse) Loopback
      5. 7.4.5 BIST Configuration
      6. 7.4.6 Cable Diagnostics
        1. 7.4.6.1 TDR
        2. 7.4.6.2 Energy Detect
        3. 7.4.6.3 Fast Link Detect
        4. 7.4.6.4 Speed Optimization
        5. 7.4.6.5 Mirror Mode
        6. 7.4.6.6 Interrupt
        7. 7.4.6.7 IEEE 802.3 Test Modes
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 LED Operation From 1.8V I/O VDD Supply
      4. 7.5.4 PHY Address Configuration
      5. 7.5.5 Reset Operation
        1. 7.5.5.1 Hardware Reset
        2. 7.5.5.2 IEEE Software Reset
        3. 7.5.5.3 Global Software Reset
        4. 7.5.5.4 Global Software Restart
      6. 7.5.6 Power-Saving Modes
        1. 7.5.6.1 IEEE Power Down
        2. 7.5.6.2 Deep Power-Down Mode
        3. 7.5.6.3 Active Sleep
        4. 7.5.6.4 Passive Sleep
    6. 7.6 Register Maps
      1. 7.6.1   Basic Mode Control Register (BMCR)
      2. 7.6.2   Basic Mode Status Register (BMSR)
      3. 7.6.3   PHY Identifier Register #1 (PHYIDR1)
      4. 7.6.4   PHY Identifier Register #2 (PHYIDR2)
      5. 7.6.5   Auto-Negotiation Advertisement Register (ANAR)
      6. 7.6.6   Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 7.6.7   Auto-Negotiate Expansion Register (ANER)
      8. 7.6.8   Auto-Negotiation Next Page Transmit Register (ANNPTR)
      9. 7.6.9   Auto-Negotiation Next Page Receive Register (ANNPRR)
      10. 7.6.10  1000BASE-T Configuration Register (CFG1)
      11. 7.6.11  Status Register 1 (STS1)
      12. 7.6.12  Extended Register Addressing
        1. 7.6.12.1 Register Control Register (REGCR)
        2. 7.6.12.2 Address or Data Register (ADDAR)
      13. 7.6.13  1000BASE-T Status Register (1KSCR)
      14. 7.6.14  PHY Control Register (PHYCR)
      15. 7.6.15  PHY Status Register (PHYSTS)
      16. 7.6.16  MII Interrupt Control Register (MICR)
      17. 7.6.17  Interrupt Status Register (ISR)
      18. 7.6.18  Configuration Register 2 (CFG2)
      19. 7.6.19  Receiver Error Counter Register (RECR)
      20. 7.6.20  BIST Control Register (BISCR)
      21. 7.6.21  Status Register 2 (STS2)
      22. 7.6.22  LED Configuration Register 1 (LEDCR1)
      23. 7.6.23  LED Configuration Register 2 (LEDCR2)
      24. 7.6.24  LED Configuration Register (LEDCR3)
      25. 7.6.25  Configuration Register 3 (CFG3)
      26. 7.6.26  Control Register (CTRL)
      27. 7.6.27  Testmode Channel Control (TMCH_CTRL)
      28. 7.6.28  Robust Auto MDIX Timer Configuration Register (AMDIX_TMR_CFG)
      29. 7.6.29  Fast Link Drop Configuration Register (FLD_CFG)
      30. 7.6.30  Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)
      31. 7.6.31  Configuration Register 4 (CFG4)
      32. 7.6.32  RGMII Control Register (RGMIICTL)
      33. 7.6.33  RGMII Control Register 2 (RGMIICTL2)
      34. 7.6.34  100BASE-TX Configuration (100CR)
      35. 7.6.35  Viterbi Module Configuration (VTM_CFG)
      36. 7.6.36  Skew FIFO Status (SKEW_FIFO)
      37. 7.6.37  Strap Configuration Status Register 1 (STRAP_STS1)
      38. 7.6.38  Strap Configuration Status Register 2 (STRAP_STS2)
      39. 7.6.39  BIST Control and Status Register 1 (BICSR1)
      40. 7.6.40  BIST Control and Status Register 2 (BICSR2)
      41. 7.6.41  BIST Control and Status Register 3 (BICSR3)
      42. 7.6.42  BIST Control and Status Register 4 (BICSR4)
      43. 7.6.43  Configuration for Receiver's Equalizer (CRE)
      44. 7.6.44  RGMII Delay Control Register (RGMIIDCTL)
      45. 7.6.45  ANA_LD_TXG_FINE_GAINSEL_AB (ALTFGAB)
      46. 7.6.46  ANA_LD_TXG_FINE_GAINSEL_CD (ALTFGCD)
      47. 7.6.47  ANA_LD_FILTER_TUNE_AB (ALFTAB)
      48. 7.6.48  ANA_LD_FILTER_TUNE_CD (ALFTCD)
      49. 7.6.49  Configuration of Receiver's LPF (CRLPF)
      50. 7.6.50  Enable Control of Receiver's Equalizer (ECRE)
      51. 7.6.51  PLL Clock-out Control Register (PLLCTL)
      52. 7.6.52  Sync FIFO Control (SYNC_FIFO_CTRL)
      53. 7.6.53  Loopback Configuration Register (LOOPCR)
      54. 7.6.54  DSP Configuration (DSP_CONFIG)
      55. 7.6.55  DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)
      56. 7.6.56  Receive Configuration Register (RXFCFG)
      57. 7.6.57  Receive Status Register (RXFSTS)
      58. 7.6.58  Pattern Match Data Register 1 (RXFPMD1)
      59. 7.6.59  Pattern Match Data Register 2 (RXFPMD2)
      60. 7.6.60  Pattern Match Data Register 3 (RXFPMD3)
      61. 7.6.61  SecureOn Pass Register 2 (RXFSOP1)
      62. 7.6.62  SecureOn Pass Register 2 (RXFSOP2)
      63. 7.6.63  SecureOn Pass Register 3 (RXFSOP3)
      64. 7.6.64  Receive Pattern Register 1 (RXFPAT1)
      65. 7.6.65  Receive Pattern Register 2 (RXFPAT2)
      66. 7.6.66  Receive Pattern Register 3 (RXFPAT3)
      67. 7.6.67  Receive Pattern Register 4 (RXFPAT4)
      68. 7.6.68  Receive Pattern Register 5 (RXFPAT5)
      69. 7.6.69  Receive Pattern Register 6 (RXFPAT6)
      70. 7.6.70  Receive Pattern Register 7 (RXFPAT7)
      71. 7.6.71  Receive Pattern Register 8 (RXFPAT8)
      72. 7.6.72  Receive Pattern Register 9 (RXFPAT9)
      73. 7.6.73  Receive Pattern Register 10 (RXFPAT10)
      74. 7.6.74  Receive Pattern Register 11 (RXFPAT11)
      75. 7.6.75  Receive Pattern Register 12 (RXFPAT12)
      76. 7.6.76  Receive Pattern Register 13 (RXFPAT13)
      77. 7.6.77  Receive Pattern Register 14 (RXFPAT14)
      78. 7.6.78  Receive Pattern Register 15 (RXFPAT15)
      79. 7.6.79  Receive Pattern Register 16 (RXFPAT16)
      80. 7.6.80  Receive Pattern Register 17 (RXFPAT17)
      81. 7.6.81  Receive Pattern Register 18 (RXFPAT18)
      82. 7.6.82  Receive Pattern Register 19 (RXFPAT19)
      83. 7.6.83  Receive Pattern Register 20 (RXFPAT20)
      84. 7.6.84  Receive Pattern Register 21 (RXFPAT21)
      85. 7.6.85  Receive Pattern Register 22 (RXFPAT22)
      86. 7.6.86  Receive Pattern Register 23 (RXFPAT23)
      87. 7.6.87  Receive Pattern Register 24 (RXFPAT24)
      88. 7.6.88  Receive Pattern Register 25 (RXFPAT25)
      89. 7.6.89  Receive Pattern Register 26 (RXFPAT26)
      90. 7.6.90  Receive Pattern Register 27 (RXFPAT27)
      91. 7.6.91  Receive Pattern Register 28 (RXFPAT28)
      92. 7.6.92  Receive Pattern Register 29 (RXFPAT29)
      93. 7.6.93  Receive Pattern Register 30 (RXFPAT30)
      94. 7.6.94  Receive Pattern Register 31 (RXFPAT31)
      95. 7.6.95  Receive Pattern Register 32 (RXFPAT32)
      96. 7.6.96  Receive Pattern Byte Mask Register 1 (RXFPBM1)
      97. 7.6.97  Receive Pattern Byte Mask Register 2 (RXFPBM2)
      98. 7.6.98  Receive Pattern Byte Mask Register 3 (RXFPBM3)
      99. 7.6.99  Receive Pattern Byte Mask Register 4 (RXFPBM4)
      100. 7.6.100 Receive Pattern Control (RXFPATC)
      101. 7.6.101 I/O Configuration (IO_MUX_CFG)
      102. 7.6.102 GPIO Mux Control Register 1 (GPIO_MUX_CTRL1)
      103. 7.6.103 GPIO Mux Control Register 2 (GPIO_MUX_CTRL2)
      104. 7.6.104 GPIO Mux Control Register (GPIO_MUX_CTRL)
      105. 7.6.105 TDR General Configuration Register 1 (TDR_GEN_CFG1)
      106. 7.6.106 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)
      107. 7.6.107 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)
      108. 7.6.108 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)
      109. 7.6.109 TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4)
      110. 7.6.110 TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5)
      111. 7.6.111 TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6)
      112. 7.6.112 TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7)
      113. 7.6.113 TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8)
      114. 7.6.114 TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9)
      115. 7.6.115 TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10)
      116. 7.6.116 TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1)
      117. 7.6.117 TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2)
      118. 7.6.118 TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3)
      119. 7.6.119 TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4)
      120. 7.6.120 TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5)
      121. 7.6.121 TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6)
      122. 7.6.122 TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7)
      123. 7.6.123 TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8)
      124. 7.6.124 TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9)
      125. 7.6.125 TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10)
      126. 7.6.126 TDR General Status (TDR_GEN_STATUS)
      127. 7.6.127 TDR Peak Sign AB (TDR_PEAK_SIGN_A_B)
      128. 7.6.128 TDR Peak Sign CD (TDR_PEAK_SIGN_C_D)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Cable Line Driver
        2. 8.2.1.2 Clock In (XI) Recommendation
        3. 8.2.1.3 Crystal Recommendations
        4. 8.2.1.4 Clock Out (CLK_OUT) Phase Noise
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 MAC Interface
          1. 8.2.2.1.1 RGMII Layout Guidelines
          2. 8.2.2.1.2 GMII Layout Guidelines
        2. 8.2.2.2 Media Dependent Interface (MDI)
          1. 8.2.2.2.1 MDI Layout Guidelines
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Signal Traces
        2. 8.4.1.2 Return Path
        3. 8.4.1.3 Transformer Layout
        4. 8.4.1.4 Metal Pour
        5. 8.4.1.5 PCB Layer Stacking
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
  • PAP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME HTQFP VQFN
MAC INTERFACES RGMII
TX_CLK 30 O MII TRANSMIT CLOCK: TX_CLK is a continuous clock signal driven by the PHY during 10Mbps or 100Mbps MII mode. TX_CLK clocks the data or error out of the MAC layer and into the PHY.
The TX_CLK clock frequency is 2.5MHz in 10BASE-Te and 25MHz in 100BASE-TX mode.
TX_D7 31 I, PD GMII TRANSMIT DATA Bit 7: This signal carries data from the MAC to the PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D6 30 I, PD GMII TRANSMIT DATA Bit 6: This signal carries data from the MAC to the PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D5 33 I, PD GMII TRANSMIT DATA Bit 5: This signal carries data from the MAC to the PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D4 34 I, PD GMII TRANSMIT DATA Bit 4: This signal carries data from the MAC to the PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D3 35 25 I, PD TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit clock TX_CLK.
TX_D2 36 26 I, PD TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit clock TX_CLK.
TX_D1 37 27 I, PD TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit clock TX_CLK.
TX_D0 38 28 I, PD TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit clock TX_CLK.
TX_ER 39 I, PD GMII TRANSMIT ERROR: This signal is used in GMII mode to force the PHY to transmit invalid symbols. The TX_ER signal is synchronous to the GMII transmit clock GTX_CLK.
In MII 4B nibble mode, assertion of Transmit Error by the controller causes the PHY to issue invalid symbols followed by Halt (H) symbols until deassertion occurs.
In GMII mode, assertion causes the PHY to emit one or more code-groups that are invalid data or delimiter in the transmitted frame.
GTX_CLK 40 29 I, PD GMII and RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125MHz.
RX_CLK 43 32 O RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation:
2.5MHz in 10Mbps mode.
25MHz in 100Mbps mode.
125MHz in 1000Mbps GMII and RGMII mode.
RX_D0 44 33 S, O, PD RECIEVE DATA Bit 0: This signal carries data from the PHY to the MAC in GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D1 45 34 O, PD RECIEVE DATA Bit 1: This signal carries data from the PHY to the MAC in GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D2 46 35 S, O, PD RECIEVE DATA Bit 2: This signal carries data from the PHY to the MAC in GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D3 47 36 O, PD RECIEVE DATA Bit 3: This signal carries data from the PHY to the MAC in GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D4 48 S, O, PD RECIEVE DATA Bit 4: This signal carries data from the PHY to the MAC in GMII mode. It is synchronous to the receive clock RX_CLK.
RX_D5 49 S, O, PD RECIEVE DATA Bit 5: This signal carries data from the PHY to the MAC in GMII mode. It is synchronous to the receive clock RX_CLK.
RX_D6 50 S, O, PD RECIEVE DATA Bit 6: This signal carries data from the PHY to the MAC in GMII mode. It is synchronous to the receive clock RX_CLK.
RX_D7 51 S, O, PD RECIEVE DATA Bit 7: This signal carries data from the PHY to the MAC in GMII mode. It is synchronous to the receive clock RX_CLK.
TX_EN / TX_CTRL 52 37 I, PD TRANSMIT ENABLE or TRANSMIT CONTROL: In MII or GMII mode,it is an active high input sourced from MAC layer to indicate transmission data is available on the TXD.
In RGMII mode, it combines the transmit enable and the transmit error signals of GMII mode using both clock edges.
RX_DV / RX_CTRL 53 38 S, O, PD RECEIVE DATA VALID or RECEIVE CONTROL: In MII and GMII modes, it is asserted high to indicate that valid data is present on the corresponding RXD[3:0] in MII mode and RXD[7:0] in GMII mode.
(Straps Required) In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK).
RX_ER / GPIO O, PD RECEIVE ERROR: In 10Mbps, 100Mbps and 1000Mbps mode this active high output indicates that the PHY has detected a Receive Error. The RX_ER signal is synchronous with the receive clock (RX_CLK).
In RGMII, the RX_ER pin is not used.
COL / GPIO O, PD COLLISION DETECT: Asserted high to indicate detection of a collision condition (assertion of CRS due to simultaneous transmit and receive activity) in Half-Duplex modes. This signal is not synchronous to either MII clock (GTX_CLK, TX_CLK or RX_CLK).
This signal is not defined and stays low for Full-Duplex modes.
In RGMII mode, COL is not used.
CRS 56 S, O, PD CARRIER SENSE: CRS is asserted high to indicate the presence of a carrier due to receive or transmit activity in Half-Duplex mode.
For 10BASE-Te and 100BASE-TX Full-Duplex operation CRS is asserted when a received packet is detected. This signal is not defined for 1000BASE-T Full-Duplex mode.
In RGMII mode, CRS is not used.
GENERAL PURPOSE I/O
GPIO_0 39 S, O, PD General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
GPIO_1 40 S, O, PD General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
MANAGEMENT INTERFACE
MDC 20 16 I, PD MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz and no minimum.
MDIO 21 17 I/O MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the management station or the PHY. This pin requires pullup resistor. The IEEE specified resistor value is 1.5kΩ, but a 2.2kΩ is acceptable.
INT / PWDN 60 44 I/O, PU INTERRUPT / POWER DOWN:
The default function of this pin is POWER DOWN.
POWER DOWN: Asserting this signal low enables the Power Down mode of operation. In this mode, the device will power down and consume minimum power. Register access will be available through the Management Interface to configure and power up the device.
INTERRUPT: This pin may be programmed as an interrupt output instead of a Power down input. In this mode, Interrupts will be asserted low using this pin. When operating this pin as an interrupt, it is an open-drain architecture. Register access is required for the pin to be used as an interrupt mechanism. When operating this pin as an interrupt, an external 2.2kΩ connected to the VDDIO supply is recommended.
RESET
RESET_N 59 43 I, PU RESET: The active low RESET initializes or re-initializes the DP83867. All internal registers will re-initialize to their default state upon assertion of RESET. The RESET input must be held low for a minimum of 1µs.
CLOCK INTERFACE
XI 19 15 I CRYSTAL/OSCILLATOR INPUT: 25MHz oscillator or crystal input (50 ppm)
XO 18 14 O CRYSTAL OUTPUT: Second terminal for 25MHz crystal. Must be left floating if a clock oscillator is used.
CLK_OUT 22 18 O CLOCK OUTPUT: Output clock
JTAG INTERFACE
JTAG_CLK 25 20 I, PU JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity.
JTAG_TDO 26 21 O JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device via TDO.
JTAG_TMS 27 22 I, PU JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction.
JTAG_TDI 28 23 I, PU JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device via TDI.
JTAG_TRSTN 24 I, PU JTAG TEST RESET: IEEE 1149.1 Test Reset pin, active low reset provides for asynchronous reset of the Tap Controller. This reset has no effect on the device registers.
LED INTERFACE
LED_2 61 45 S, I/O, PD LED_2: By default, this pin indicates receive or transmit activity. Additional functionality is configurable via LEDCR1[11:8] register bits.
NOTE: This pin is a Strap Configuration pin for RGZ devices only.
LED_1 62 46 S, I/O, PD LED_1: By default, this pin indicates that 1000BASE-T link is established. Additional functionality is configurable via LEDCR1[7:4] register bits.
LED_0 63 47 S, I/O, PD LED_0: By default, this pin indicates that link is established. Additional functionality is configurable via LEDCR1[3:0] register bits.
MEDIA DEPENDENT INTERFACE
TD_P_A 2 1 A Differential Transmit and Receive Signals
TD_M_A 3 2 A Differential Transmit and Receive Signals
TD_P_B 5 4 A Differential Transmit and Receive Signals
TD_M_B 6 5 A Differential Transmit and Receive Signals
TD_P_C 10 7 A Differential Transmit and Receive Signals
TD_M_C 11 8 A Differential Transmit and Receive Signals
TD_P_D 13 10 A Differential Transmit and Receive Signals
TD_M_D 14 11 A Differential Transmit and Receive Signals
OTHER PINS
Reserved 1, 7, 9, 16 A Reserved
RBIAS 15 12 A Bias Resistor Connection. A 11kΩ +/-1% resistor should be connected from RBIAS to GND.
POWER AND GROUND PINS
VDDIO 23, 41, 57 19, 30, 41 P I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1µF & 0.1µF capacitor to GND
VDDA1P8 17, 64 13, 48 P 1.8V Analog Supply (+/-5%).
No external supply is required for this pin. When unused, no connections should be made to this pin.
For additional power savings, an external 1.8V supply can be connected to these pins. When using an external supply, each pin requires a 1µF & 0.1µF capacitor to GND.
VDDA2P5 4, 12 3, 9 P 2.5V Analog Supply (+/-5%). Each pin requires a 1µF & 0.1µF capacitor to GND
VDD1P1 8, 29, 42, 58 P 1.1V Analog Supply (+/-5%). Each pin requires a 1µF & 0.1µF capacitor to GND
VDD1P0 6, 24, 31, 42 P 1.0V Analog Supply (+15.5%,-5%). Each pin requires a 1µF & 0.1µF capacitor to GND
GND Die Attach Pad Die Attach Pad P Ground
(1)

The functionality of the pins are defined below.

  • Type I: Input
  • Type O: Output
  • Type I/O: Input /Output
  • Type PD or PU: Internal Pull-down or Pull-up
  • Type S: Strap Configuration Pin
  • Type: A Analog pins