SNLS484H February   2015  – June 2024 DP83867CR , DP83867IR

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1.     7
    2. 5.1 Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Power-Up Timing
    7. 6.7  Reset Timing
    8. 6.8  MII Serial Management Timing
    9. 6.9  RGMII Timing
    10. 6.10 GMII Transmit Timing
    11. 6.11 GMII Receive Timing
    12. 6.12 100Mbps MII Transmit Timing
    13. 6.13 100Mbps MII Receive Timing #GUID-033E0939-17C5-4DC1-9C2C-A3998C85D8B1/SNLS4845065
    14. 6.14 10Mbps MII Transmit Timing
    15. 6.15 10Mbps MII Receive Timing
    16. 6.16 DP83867IR/CR Start of Frame Detection Timing
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 WoL (Wake-on-LAN) Packet Detection
        1. 7.3.1.1 Magic Packet Structure
        2. 7.3.1.2 Magic Packet Example
        3. 7.3.1.3 Wake-on-LAN Configuration and Status
      2. 7.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 7.3.2.1 SFD Latency Variation and Determinism
          1. 7.3.2.1.1 1000Mb SFD Variation in Master Mode
          2. 7.3.2.1.2 1000Mb SFD Variation in Slave Mode
          3. 7.3.2.1.3 100Mb SFD Variation
      3. 7.3.3 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 MAC Interfaces
        1. 7.4.1.1 Reduced GMII (RGMII)
          1. 7.4.1.1.1 1000Mbps Mode Operation
          2. 7.4.1.1.2 1000Mbps Mode Timing
          3. 7.4.1.1.3 10- and 100Mbps Mode
        2. 7.4.1.2 Gigabit MII (GMII)
        3. 7.4.1.3 Media Independent Interface (MII)
          1. 7.4.1.3.1 Nibble-wide MII Data Interface
          2. 7.4.1.3.2 Collision Detect
          3. 7.4.1.3.3 Carrier Sense
      2. 7.4.2 Serial Management Interface
        1. 7.4.2.1 Extended Address Space Access
          1. 7.4.2.1.1 Write Address Operation
          2. 7.4.2.1.2 Read Address Operation
          3. 7.4.2.1.3 Write (No Post Increment) Operation
          4. 7.4.2.1.4 Read (No Post Increment) Operation
          5. 7.4.2.1.5 Write (Post Increment) Operation
          6. 7.4.2.1.6 Read (Post Increment) Operation
          7. 7.4.2.1.7 Example of Read Operation Using Indirect Register Access
          8. 7.4.2.1.8 Example of Write Operation Using Indirect Register Access
      3. 7.4.3 Auto-Negotiation
        1. 7.4.3.1 Speed and Duplex Selection - Priority Resolution
        2. 7.4.3.2 Master and Slave Resolution
        3. 7.4.3.3 Pause and Asymmetrical Pause Resolution
        4. 7.4.3.4 Next Page Support
        5. 7.4.3.5 Parallel Detection
        6. 7.4.3.6 Restart Auto-Negotiation
        7. 7.4.3.7 Enabling Auto-Negotiation Through Software
        8. 7.4.3.8 Auto-Negotiation Complete Time
        9. 7.4.3.9 Auto-MDIX Resolution
      4. 7.4.4 Loopback Mode
        1. 7.4.4.1 Near-End Loopback
          1. 7.4.4.1.1 MII Loopback
          2. 7.4.4.1.2 PCS Loopback
          3. 7.4.4.1.3 Digital Loopback
          4. 7.4.4.1.4 Analog Loopback
        2. 7.4.4.2 External Loopback
        3. 7.4.4.3 Far-End (Reverse) Loopback
      5. 7.4.5 BIST Configuration
      6. 7.4.6 Cable Diagnostics
        1. 7.4.6.1 TDR
        2. 7.4.6.2 Energy Detect
        3. 7.4.6.3 Fast Link Detect
        4. 7.4.6.4 Speed Optimization
        5. 7.4.6.5 Mirror Mode
        6. 7.4.6.6 Interrupt
        7. 7.4.6.7 IEEE 802.3 Test Modes
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 LED Operation From 1.8V I/O VDD Supply
      4. 7.5.4 PHY Address Configuration
      5. 7.5.5 Reset Operation
        1. 7.5.5.1 Hardware Reset
        2. 7.5.5.2 IEEE Software Reset
        3. 7.5.5.3 Global Software Reset
        4. 7.5.5.4 Global Software Restart
      6. 7.5.6 Power-Saving Modes
        1. 7.5.6.1 IEEE Power Down
        2. 7.5.6.2 Deep Power-Down Mode
        3. 7.5.6.3 Active Sleep
        4. 7.5.6.4 Passive Sleep
    6. 7.6 Register Maps
      1. 7.6.1   Basic Mode Control Register (BMCR)
      2. 7.6.2   Basic Mode Status Register (BMSR)
      3. 7.6.3   PHY Identifier Register #1 (PHYIDR1)
      4. 7.6.4   PHY Identifier Register #2 (PHYIDR2)
      5. 7.6.5   Auto-Negotiation Advertisement Register (ANAR)
      6. 7.6.6   Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 7.6.7   Auto-Negotiate Expansion Register (ANER)
      8. 7.6.8   Auto-Negotiation Next Page Transmit Register (ANNPTR)
      9. 7.6.9   Auto-Negotiation Next Page Receive Register (ANNPRR)
      10. 7.6.10  1000BASE-T Configuration Register (CFG1)
      11. 7.6.11  Status Register 1 (STS1)
      12. 7.6.12  Extended Register Addressing
        1. 7.6.12.1 Register Control Register (REGCR)
        2. 7.6.12.2 Address or Data Register (ADDAR)
      13. 7.6.13  1000BASE-T Status Register (1KSCR)
      14. 7.6.14  PHY Control Register (PHYCR)
      15. 7.6.15  PHY Status Register (PHYSTS)
      16. 7.6.16  MII Interrupt Control Register (MICR)
      17. 7.6.17  Interrupt Status Register (ISR)
      18. 7.6.18  Configuration Register 2 (CFG2)
      19. 7.6.19  Receiver Error Counter Register (RECR)
      20. 7.6.20  BIST Control Register (BISCR)
      21. 7.6.21  Status Register 2 (STS2)
      22. 7.6.22  LED Configuration Register 1 (LEDCR1)
      23. 7.6.23  LED Configuration Register 2 (LEDCR2)
      24. 7.6.24  LED Configuration Register (LEDCR3)
      25. 7.6.25  Configuration Register 3 (CFG3)
      26. 7.6.26  Control Register (CTRL)
      27. 7.6.27  Testmode Channel Control (TMCH_CTRL)
      28. 7.6.28  Robust Auto MDIX Timer Configuration Register (AMDIX_TMR_CFG)
      29. 7.6.29  Fast Link Drop Configuration Register (FLD_CFG)
      30. 7.6.30  Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)
      31. 7.6.31  Configuration Register 4 (CFG4)
      32. 7.6.32  RGMII Control Register (RGMIICTL)
      33. 7.6.33  RGMII Control Register 2 (RGMIICTL2)
      34. 7.6.34  100BASE-TX Configuration (100CR)
      35. 7.6.35  Viterbi Module Configuration (VTM_CFG)
      36. 7.6.36  Skew FIFO Status (SKEW_FIFO)
      37. 7.6.37  Strap Configuration Status Register 1 (STRAP_STS1)
      38. 7.6.38  Strap Configuration Status Register 2 (STRAP_STS2)
      39. 7.6.39  BIST Control and Status Register 1 (BICSR1)
      40. 7.6.40  BIST Control and Status Register 2 (BICSR2)
      41. 7.6.41  BIST Control and Status Register 3 (BICSR3)
      42. 7.6.42  BIST Control and Status Register 4 (BICSR4)
      43. 7.6.43  Configuration for Receiver's Equalizer (CRE)
      44. 7.6.44  RGMII Delay Control Register (RGMIIDCTL)
      45. 7.6.45  ANA_LD_TXG_FINE_GAINSEL_AB (ALTFGAB)
      46. 7.6.46  ANA_LD_TXG_FINE_GAINSEL_CD (ALTFGCD)
      47. 7.6.47  ANA_LD_FILTER_TUNE_AB (ALFTAB)
      48. 7.6.48  ANA_LD_FILTER_TUNE_CD (ALFTCD)
      49. 7.6.49  Configuration of Receiver's LPF (CRLPF)
      50. 7.6.50  Enable Control of Receiver's Equalizer (ECRE)
      51. 7.6.51  PLL Clock-out Control Register (PLLCTL)
      52. 7.6.52  Sync FIFO Control (SYNC_FIFO_CTRL)
      53. 7.6.53  Loopback Configuration Register (LOOPCR)
      54. 7.6.54  DSP Configuration (DSP_CONFIG)
      55. 7.6.55  DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)
      56. 7.6.56  Receive Configuration Register (RXFCFG)
      57. 7.6.57  Receive Status Register (RXFSTS)
      58. 7.6.58  Pattern Match Data Register 1 (RXFPMD1)
      59. 7.6.59  Pattern Match Data Register 2 (RXFPMD2)
      60. 7.6.60  Pattern Match Data Register 3 (RXFPMD3)
      61. 7.6.61  SecureOn Pass Register 2 (RXFSOP1)
      62. 7.6.62  SecureOn Pass Register 2 (RXFSOP2)
      63. 7.6.63  SecureOn Pass Register 3 (RXFSOP3)
      64. 7.6.64  Receive Pattern Register 1 (RXFPAT1)
      65. 7.6.65  Receive Pattern Register 2 (RXFPAT2)
      66. 7.6.66  Receive Pattern Register 3 (RXFPAT3)
      67. 7.6.67  Receive Pattern Register 4 (RXFPAT4)
      68. 7.6.68  Receive Pattern Register 5 (RXFPAT5)
      69. 7.6.69  Receive Pattern Register 6 (RXFPAT6)
      70. 7.6.70  Receive Pattern Register 7 (RXFPAT7)
      71. 7.6.71  Receive Pattern Register 8 (RXFPAT8)
      72. 7.6.72  Receive Pattern Register 9 (RXFPAT9)
      73. 7.6.73  Receive Pattern Register 10 (RXFPAT10)
      74. 7.6.74  Receive Pattern Register 11 (RXFPAT11)
      75. 7.6.75  Receive Pattern Register 12 (RXFPAT12)
      76. 7.6.76  Receive Pattern Register 13 (RXFPAT13)
      77. 7.6.77  Receive Pattern Register 14 (RXFPAT14)
      78. 7.6.78  Receive Pattern Register 15 (RXFPAT15)
      79. 7.6.79  Receive Pattern Register 16 (RXFPAT16)
      80. 7.6.80  Receive Pattern Register 17 (RXFPAT17)
      81. 7.6.81  Receive Pattern Register 18 (RXFPAT18)
      82. 7.6.82  Receive Pattern Register 19 (RXFPAT19)
      83. 7.6.83  Receive Pattern Register 20 (RXFPAT20)
      84. 7.6.84  Receive Pattern Register 21 (RXFPAT21)
      85. 7.6.85  Receive Pattern Register 22 (RXFPAT22)
      86. 7.6.86  Receive Pattern Register 23 (RXFPAT23)
      87. 7.6.87  Receive Pattern Register 24 (RXFPAT24)
      88. 7.6.88  Receive Pattern Register 25 (RXFPAT25)
      89. 7.6.89  Receive Pattern Register 26 (RXFPAT26)
      90. 7.6.90  Receive Pattern Register 27 (RXFPAT27)
      91. 7.6.91  Receive Pattern Register 28 (RXFPAT28)
      92. 7.6.92  Receive Pattern Register 29 (RXFPAT29)
      93. 7.6.93  Receive Pattern Register 30 (RXFPAT30)
      94. 7.6.94  Receive Pattern Register 31 (RXFPAT31)
      95. 7.6.95  Receive Pattern Register 32 (RXFPAT32)
      96. 7.6.96  Receive Pattern Byte Mask Register 1 (RXFPBM1)
      97. 7.6.97  Receive Pattern Byte Mask Register 2 (RXFPBM2)
      98. 7.6.98  Receive Pattern Byte Mask Register 3 (RXFPBM3)
      99. 7.6.99  Receive Pattern Byte Mask Register 4 (RXFPBM4)
      100. 7.6.100 Receive Pattern Control (RXFPATC)
      101. 7.6.101 I/O Configuration (IO_MUX_CFG)
      102. 7.6.102 GPIO Mux Control Register 1 (GPIO_MUX_CTRL1)
      103. 7.6.103 GPIO Mux Control Register 2 (GPIO_MUX_CTRL2)
      104. 7.6.104 GPIO Mux Control Register (GPIO_MUX_CTRL)
      105. 7.6.105 TDR General Configuration Register 1 (TDR_GEN_CFG1)
      106. 7.6.106 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)
      107. 7.6.107 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)
      108. 7.6.108 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)
      109. 7.6.109 TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4)
      110. 7.6.110 TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5)
      111. 7.6.111 TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6)
      112. 7.6.112 TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7)
      113. 7.6.113 TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8)
      114. 7.6.114 TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9)
      115. 7.6.115 TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10)
      116. 7.6.116 TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1)
      117. 7.6.117 TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2)
      118. 7.6.118 TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3)
      119. 7.6.119 TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4)
      120. 7.6.120 TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5)
      121. 7.6.121 TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6)
      122. 7.6.122 TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7)
      123. 7.6.123 TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8)
      124. 7.6.124 TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9)
      125. 7.6.125 TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10)
      126. 7.6.126 TDR General Status (TDR_GEN_STATUS)
      127. 7.6.127 TDR Peak Sign AB (TDR_PEAK_SIGN_A_B)
      128. 7.6.128 TDR Peak Sign CD (TDR_PEAK_SIGN_C_D)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Cable Line Driver
        2. 8.2.1.2 Clock In (XI) Recommendation
        3. 8.2.1.3 Crystal Recommendations
        4. 8.2.1.4 Clock Out (CLK_OUT) Phase Noise
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 MAC Interface
          1. 8.2.2.1.1 RGMII Layout Guidelines
          2. 8.2.2.1.2 GMII Layout Guidelines
        2. 8.2.2.2 Media Dependent Interface (MDI)
          1. 8.2.2.2.1 MDI Layout Guidelines
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Signal Traces
        2. 8.4.1.2 Return Path
        3. 8.4.1.3 Transformer Layout
        4. 8.4.1.4 Metal Pour
        5. 8.4.1.5 PCB Layer Stacking
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
  • PAP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1 Strap Configuration

The DP83867 uses many of the functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap options are internally reloaded from the values sampled at power up or hard reset. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

The strap pins supported are 4-level straps, which are described in greater detail below.

Note:

Because strap pins may have alternate functions after reset is deasserted, they should not be connected directly to VDD or GND.

Configuration of the device may be done through the 4-level strap pins or through the management register interface. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the 4-level strap pin input and the supply to select one of the possible selected modes.

The MAC interface pins must support I/O voltages of 3.3V, 2.5V, and 1.8V. As the strap inputs are implemented on these pins, the straps must also support operation at 3.3V, 2.5V, and 1.8V supplies.

For more information about configuring 4-level straps, see the Configuring Ethernet Devices with 4-Level Straps application report (SNLA258).

DP83867IR DP83867CR Strap Circuit Figure 7-12 Strap Circuit
Table 7-4 4-Level Strap Resistor Ratios
MODETARGET VOLTAGEIDEAL Rhi (kΩ)IDEAL Rlo (kΩ)
Vmin (V)Vtyp (V)Vmax (V)
1000.098 × VDDIOOPENOPEN
20.140 × VDDIO0.165 × VDDIO0.191 × VDDIO102.49
30.225 × VDDIO0.255 × VDDIO0.284 × VDDIO5.762.49
40.694 × VDDIO0.783 × VDDIO0.888 × VDDIO2.49OPEN

All straps have a 9kΩ ±25% internal pulldown resistor. The voltage at strap pins should be between the Vmin and Vmax mentioned in the Target Voltage column in Table 7-4. Strap resistors with 1% tolerance are recommended.

The following tables describes the DP83867 configuration straps:

Table 7-5 4-Level Strap Pins
PIN NAME64 HTQFP PIN #48 QFN PIN #DEFAULTSTRAP FUNCTION
RX_D04433[00]MODEPHY_ADD1PHY_ADD0
100
201
310
411
RX_D24635[00]MODEPHY_ADD3PHY_ADD2
100
201
310
411
RX_D448[00]MODEANEG_SEL1PHY_ADD4
100
201
310
411
RX_D549[00]MODEForce MDI/XHalf-Duplex Enable (FD/HD)
100
201
310
411
RX_D650[00]MODERGMII DisableAMDIX Disable
100
201
310
411
RX_D751[00]MODESpeed Optimization EnableClock Out Disable
100
201
310
411
RX_DV/RX_CTRL(2)5338[0]MODEAutoneg Disable
1N/A
(Straps Required)2N/A
30
41
CRS(3)56[0]MODEFast Link Drop (FLD)
10
21
3N/A
4N/A
LED_2(1)45[00]MODERGMII Clock Skew TX[1]RGMII Clock Skew TX[0]
100
201
310
411
LED_1 (RGZ)46[00]MODEANEG_SELRGMII Clock Skew TX[2]
100
201
310
411
LED_1 (PAP)62[0]MODEANEG_SEL0
10
20
31
41
LED_0(4)6347[0]MODEMirror Enable
10
2N/A
31
4N/A
GPIO_0(1)39[00]MODERGMII Clock Skew RX[0]
10
2Not Applicable
31
4Not Applicable
GPIO_140[00]MODERGMII Clock Skew RX[2]RGMII Clock Skew RX[1]
100
201
310
411
(1) RGMII TX and RX DLL Skew straps are only available on RGZ devices.
(2) Strap modes 1 and 2 are not applicable for RX_DV/RX_CTRL. The RX_DV/RX_CTRL strap must be configured for strap mode 3 or strap mode 4. If the RX_CTRL pin cannot be strapped to mode 3 or mode 4, bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. Autoneg Disable should always be set to 0 when using gigabit Ethernet.
(3) Strap modes 3 and 4 are not applicable for CRS. The CRS strap must be configured for strap mode 1 or strap mode 2.
(4) Strap modes 2 and 4 are not applicable for LED_0. The LED_0 strap must be configured for strap mode 1 or strap mode 3.
Table 7-6 PAP Auto-negotiation Select Strap Details
MODEANEG_SEL0ANEG_SEL1REMARKS
10/100/100000advertise ability of 10/100/1000
100/100010advertise ability of 100/1000 only
100001advertise ability of 1000 only
10/10011advertise ability of 10/100 only
Table 7-7 RGZ Auto-negotiation Select Strap Details
MODE ANEG_SEL REMARKS
10/100/1000 0 advertise ability of 10/100/1000
100/1000 1 advertise ability of 100/1000 only
Table 7-8 RGZ RGMII Transmit Clock Skew Details
MODE RGMII CLOCK SKEW TX[2] RGMII CLOCK SKEW TX[1] RGMII CLOCK SKEW TX[0] RGMII TX CLOCK SKEW
1 0 0 0 2.0ns
2 0 0 1 1.5ns
3 0 1 0 1.0ns
4 0 1 1 0.5ns
5 1 0 0 0ns
6 1 0 1 3.5ns
7 1 1 0 3.0ns
8 1 1 1 2.5ns
Table 7-9 RGZ RGMII Receive Clock Skew Details
MODE RGMII CLOCK SKEW RX[2] RGMII CLOCK SKEW RX[1] RGMII CLOCK SKEW RX[0] RGMII RX CLOCK SKEW
1 0 0 0 2.0ns
2 0 0 1 1.5ns
3 0 1 0 1.0ns
4 0 1 1 0.5ns
5 1 0 0 0ns
6 1 0 1 3.5ns
7 1 1 0 3.0ns
8 1 1 1 2.5ns