SNLS742A September   2023  – April 2024 DP83TC811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
    2. 5.2 Pin Multiplexing
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wake-on-LAN (WoL) Packet Detection
        1. 7.3.1.1 Magic Packet Structure
        2. 7.3.1.2 Magic Packet Example
        3. 7.3.1.3 Wake-on-LAN Configuration and Status
      2. 7.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
      3. 7.3.3 Diagnostic Tool Kit
        1. 7.3.3.1 Signal Quality Indicator
        2. 7.3.3.2 Electrostatic Discharge Sensing
        3. 7.3.3.3 Time Domain Reflectometry
        4. 7.3.3.4 Temperature and Voltage Sensing
        5. 7.3.3.5 Built-In Self-Test
        6. 7.3.3.6 Loopback Modes
          1. 7.3.3.6.1 xMII Loopback
          2. 7.3.3.6.2 PCS Loopback
          3. 7.3.3.6.3 Analog Loopback
          4. 7.3.3.6.4 Reverse Loopback
      4. 7.3.4 Compliance Test Modes
        1. 7.3.4.1 Test Mode 1
        2. 7.3.4.2 Test Mode 2
        3. 7.3.4.3 Test Mode 4
        4. 7.3.4.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Down
      2. 7.4.2  Reset
      3. 7.4.3  Disable
      4. 7.4.4  Standby
      5. 7.4.5  Normal
      6. 7.4.6  Sleep Request
      7. 7.4.7  Silent
      8. 7.4.8  Sleep
      9. 7.4.9  Low-Power Sleep
      10. 7.4.10 Wake-Up
      11. 7.4.11 State Transitions
        1. 7.4.11.1 State Transition #1 - Standby to Normal
        2. 7.4.11.2 55
        3. 7.4.11.3 State Transition #2 - Normal to Standby
        4. 7.4.11.4 State Transition #3 - Normal to Sleep Request
        5. 7.4.11.5 State Transition #4 - Sleep Request to Normal
        6. 7.4.11.6 State Transition #5 - Sleep Request to Standby
        7. 7.4.11.7 State Transition #6 - Sleep Request to Silent
        8. 7.4.11.8 State Transition #7 - Silent to Standby
        9. 7.4.11.9 State Transition #8 - Silent to Sleep
      12. 7.4.12 Media Dependent Interface
        1. 7.4.12.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 7.4.12.2 Auto-Polarity Detection and Correction
        3. 7.4.12.3 Jabber Detection
        4. 7.4.12.4 Interleave Detection
      13. 7.4.13 MAC Interfaces
        1. 7.4.13.1 Media Independent Interface
        2. 7.4.13.2 Reduced Media Independent Interface
        3. 7.4.13.3 Reduced Gigabit Media Independent Interface
        4. 7.4.13.4 Serial Gigabit Media Independent Interface
      14. 7.4.14 Serial Management Interface
      15. 7.4.15 Direct Register Access
      16. 7.4.16 Extended Register Space Access
      17. 7.4.17 Write Address Operation
        1. 7.4.17.1 MMD1 - Write Address Operation
      18. 7.4.18 Read Address Operation
        1. 7.4.18.1 MMD1 - Read Address Operation
      19. 7.4.19 Write Operation (No Post Increment)
        1. 7.4.19.1 MMD1 - Write Operation (No Post Increment)
      20. 7.4.20 Read Operation (No Post Increment)
        1. 7.4.20.1 MMD1 - Read Operation (No Post Increment)
      21. 7.4.21 Write Operation (Post Increment)
        1. 7.4.21.1 MMD1 - Write Operation (Post Increment)
      22. 7.4.22 Read Operation (Post Increment)
        1. 7.4.22.1 MMD1 - Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
    6. 7.6 Register Maps
      1. 7.6.1   Register Access Summary
      2. 7.6.2   BMCR Register 0x0000 – Basic Mode Control Register
      3. 7.6.3   BMSR Register 0x0001 – Basic Mode Status Register
      4. 7.6.4   PHYID1 Register 0x0002 – PHY Identifier Register #1
      5. 7.6.5   PHYID2 Register 0x0003 – PHY Identifier Register #2
      6. 7.6.6   SGMII_CFG Register 0x0009 – SGMII Configuration Register
      7. 7.6.7   REGCR Register 0x000D – Register Control Register
      8. 7.6.8   ADDAR Register 0x000E – Address/Data Register
      9. 7.6.9   INT_TEST Register 0x0011 – Interrupt Test Register
      10. 7.6.10  INT_STAT1 Register 0x0012 – Interrupt Status Register #1
      11. 7.6.11  INT_STAT2 Register 0x0013 – Interrupt Status Register #2
      12. 7.6.12  FCSCR Register 0x0014 – False Carrier Sense Counter Register
      13. 7.6.13  RECR Register 0x0015 – Receive Error Count Register
      14. 7.6.14  BISTCR Register 0x0016 – BIST Control Register
      15. 7.6.15  xMII_CTRL Register 0x0017 – xMII Control Register
      16. 7.6.16  INT_STAT3 Register 0x0018 – Interrupt Status Register #3
      17. 7.6.17  BICTSR1 Register 0x001B – BIST Control and Status Register #1
      18. 7.6.18  BICTSR2 Register 0x001C – BIST Control and Status Register #2
      19. 7.6.19  TDR Register 0x001E – Time Domain Reflectometry Register
      20. 7.6.20  PHYRCR Register 0x001F – PHY Reset Control Register
      21. 7.6.21  LSR Register 0x0133 – Link Status Results Register
      22. 7.6.22  TDRR Register 0x016B – TDR Results Register
      23. 7.6.23  TDRLR1 Register 0x0180 – TDR Location Result Register #1
      24. 7.6.24  TDRLR2 Register 0x0181 – TDR Location Result Register #2
      25. 7.6.25  TDRPT Register 0x018A – TDR Peak Type Register
      26. 7.6.26  AUTO_PHY Register 0x018B – Autonomous PHY Control Register
      27. 7.6.27  PWRM Register 0x018C – Power Mode Register
      28. 7.6.28  SNR Register 0x0197 – Signal-to-Noise Ratio Result Register
      29. 7.6.29  SQI Register 0x0198 – Signal Quality Indication Register
      30. 7.6.30  LD_CTRL Register 0x0400 – Line Driver Control Register
      31. 7.6.31  LDG_CTRL1 Register 0x0401 – Line Driver Gain Control Register #1
      32. 7.6.32  SGMII_CTRL1 Register 0x0432 – SGMII Control Register #1
      33. 7.6.33  DLL_CTRL 0x0446 – RGMII DLL Control Register
      34. 7.6.34  ESDS Register 0x0448 – Electrostatic Discharge Status Register
      35. 7.6.35  SGMII_AUTO_TIMER Register 0x0456 – SGMII Auto-Negotiation Timer Configuration Register
      36. 7.6.36  SGMII_STAT Register 0x0459 – SGMII Auto-Negotiation Status Register
      37. 7.6.37  LED_CFG1 Register 0x0460 – LED Configuration Register #1
      38. 7.6.38  xMII_IMP_CTRL Register 0x0461 – xMII Impedance Control Register
      39. 7.6.39  IO_CTRL1 Register 0x0462 – GPIO Control Register #1
      40. 7.6.40  IO_CTRL2 Register 0x0463 – GPIO Control Register #2
      41. 7.6.41  STRAP Register 0x0467 – Strap Configuration Register
      42. 7.6.42  LED_CFG2 Register 0x0469 – LED Configuration Register #2
      43. 7.6.43  PLR_CFG Register 0x0475 – Polarity Auto-Correction Configuration Register
      44. 7.6.44  MON_CFG1 Register 0x0480 – Monitor Configuration Register #1
      45. 7.6.45  MON_CFG2 Register 0x0481 – Monitor Configuration Register #2
      46. 7.6.46  MON_CFG3 Register 0x0482 – Monitor Configuration Register #3
      47. 7.6.47  MON_STAT1 Register 0x0483 – Monitor Status Register #1
      48. 7.6.48  MON_STAT2 Register 0x0484 – Monitor Status Register #2
      49. 7.6.49  PCS_CTRL1 Register 0x0485 – PCS Control Register #1
      50. 7.6.50  PCS_CTRL2 Register – 0x0486 PCS Control Register #2
      51. 7.6.51  LPS_CTRL2 Register 0x0487 – LPS Control Register #2
      52. 7.6.52  INTER_CFG Register 0x0489 – Interleave Configuration
      53. 7.6.53  LPS_CTRL3 Register 0x0493 – LPS Control Register #3
      54. 7.6.54  JAB_CFG Register 0x0496 – Jabber Configuration Register
      55. 7.6.55  TEST_MODE_CTRL Register 0x0497 – Test Mode Control Register
      56. 7.6.56  WOL_CFG Register 0x04A0 – WoL Configuration Register
      57. 7.6.57  WOL_STAT Register 0x04A1 – WoL Status Register
      58. 7.6.58  WOL_DA1 Register 0x04A2 – WoL Destination Address Configuration Register #1
      59. 7.6.59  WOL_DA2 Register 0x04A3 – WoL Destination Address Configuration Register #2
      60. 7.6.60  WOL_DA3 Register 0x04A4 – WoL Destination Address Configuration Register #3
      61. 7.6.61  RXSOP1 Register 0x04A5 – Receive Secure-ON Password Register #1
      62. 7.6.62  RXSOP2 Register 0x04A6 – Receive Secure-ON Password Register #2
      63. 7.6.63  RXSOP3 Register 0x04A7 – Receive Secure-ON Password Register #3
      64. 7.6.64  RXPAT1 Register 0x04A8 – Receive Pattern Register #1
      65. 7.6.65  RXPAT2 Register 0x04A9 – Receive Pattern Register #2
      66. 7.6.66  RXPAT3 Register 0x04AA – Receive Pattern Register #3
      67. 7.6.67  RXPAT4 Register 0x04AB – Receive Pattern Register #4
      68. 7.6.68  RXPAT5 Register 0x04AC – Receive Pattern Register #5
      69. 7.6.69  RXPAT6 Register 0x04AD – Receive Pattern Register #6
      70. 7.6.70  RXPAT7 Register 0x04AE – Receive Pattern Register #7
      71. 7.6.71  RXPAT8 Register 0x04AF – Receive Pattern Register #8
      72. 7.6.72  RXPAT9 Register 0x04B0 – Receive Pattern Register #9
      73. 7.6.73  RXPAT10 Register 0x04B1 – Receive Pattern Register #10
      74. 7.6.74  RXPAT11 Register 0x04B2 Receive Pattern Register #11
      75. 7.6.75  RXPAT12 Register 0x04B3 – Receive Pattern Register #12
      76. 7.6.76  RXPAT13 Register 0x04B4 – Receive Pattern Register #13
      77. 7.6.77  RXPAT14 Register 0x04B5 – Receive Pattern Register #14
      78. 7.6.78  RXPAT15 Register 0x04B6 – Receive Pattern Register #15
      79. 7.6.79  RXPAT16 Register 0x04B7 – Receive Pattern Register #16
      80. 7.6.80  RXPAT17 Register 0x04B8 – Receive Pattern Register #17
      81. 7.6.81  RXPAT18 Register 0x04B9 – Receive Pattern Register #18
      82. 7.6.82  RXPAT19 Register 0x04BA Receive Pattern Register #19
      83. 7.6.83  RXPAT20 Register 0x04BB – Receive Pattern Register #20
      84. 7.6.84  RXPAT21 Register 0x04BC – Receive Pattern Register #21
      85. 7.6.85  RXPAT22 Register 0x04BD – Receive Pattern Register #22
      86. 7.6.86  RXPAT23 Register 0x04BE – Receive Pattern Register #23
      87. 7.6.87  RXPAT24 Register 0x04BF – Receive Pattern Register #24
      88. 7.6.88  RXPAT25 Register 0x04C0 – Receive Pattern Register #25
      89. 7.6.89  RXPAT26 Register 0x04C1 – Receive Pattern Register #26
      90. 7.6.90  RXPAT27 Register 0x04C2 Receive Pattern Register #27
      91. 7.6.91  RXPAT28 Register 0x04C3 – Receive Pattern Register #28
      92. 7.6.92  RXPAT29 Register 0x04C4 – Receive Pattern Register #29
      93. 7.6.93  RXPAT30 Register 0x04C5 – Receive Pattern Register #30
      94. 7.6.94  RXPAT31 Register 0x04C6 – Receive Pattern Register #31
      95. 7.6.95  RXPAT32 Register 0x04C7 – Receive Pattern Register #32
      96. 7.6.96  RXPBM1 Register 0x04C8 – Receive Pattern Byte Mask Register #1
      97. 7.6.97  RXPBM2 Register 0x04C9 – Receive Pattern Byte Mask Register #2
      98. 7.6.98  RXPBM3 Register 0x04CA – Receive Pattern Byte Mask Register #3
      99. 7.6.99  RXPBM4 Register 0x04CB – Receive Pattern Byte Mask Register #4
      100. 7.6.100 RXPATC Register 0x04CC – Receive Pattern Control Register
      101. 7.6.101 RXD3CLK Register 0x04E0 – RX_D3 Clock Control Register
      102. 7.6.102 LPS_CFG Register 0x04E5 – LPS Configuration Register
      103. 7.6.103 195
      104. 7.6.104 PMA_CTRL1 Register 0x0007 – MMD1 PMA Control Register #1
      105. 7.6.105 PMA_EXT1 Register 0x000B – MMD1 PMA Extended Ability Register #1
      106. 7.6.106 PMA_EXT2 Register 0x0012 – MMD1 PMA Extended Ability Register #2
      107. 7.6.107 PMA_CTRL2 Register 0x0834 – MMD1 PMA Control Register #2
      108. 7.6.108 TEST_CTRL Register 0x0836 – MMD1 100BASE-T1 PMA Test Control Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Physical Medium Attachment
          1. 8.2.1.1.1 Common-Mode Choke Recommendations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 Signal Traces
        2. 8.3.1.2 Return Path
        3. 8.3.1.3 Metal Pour
        4. 8.3.1.4 PCB Layer Stacking
      2. 8.3.2 Layout Example
    4. 8.4 Power Supply Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
    5. 9.5 Trademarks
  11. 10Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Pin Functions

Table 5-1 Pin Functions (2)
PINSTATE(1)DESCRIPTION
NAMENO.
MAC INTERFACE

RX_D

3
RX_M

23S, PD, O

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A data nibble, RX_D[3:0], is transmitted in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII mode. RX_D[3:2] are not used when in RMII mode.

If the PHY is bootstrapped to RMII Master mode, a 50MHz clock reference is automatically outputted on RX_D3. This clock should be fed to the MAC.

RX_M / RX_P: Differential SGMII Data Output. These pins transmit data from the PHY to the MAC. This data is synchronous to the differential SGMII clock output.

RXCLK_M / RXCLK_P: Differential SGMII Clock Output. This signal is a continuous 625MHz clock signal driven by the PHY in 6-wire SGMII mode. (configurable through register access)

RX_D2
RX_P

24

RX_D1
RXCLK_M

25

RX_D0
RXCLK_P

26
RX_CLK27O

Receive Clock: In MII and RGMII modes, the receive clock provides a 25MHz reference clock.

Unused in RMII and SGMII modes

RX_ER14S, PD, O

Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected within a received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required to be used by the MAC in MII or RMII because the PHY will automatically corrupt data on a receive error.

Unused in RGMII and SGMII modes

RX_DV
CRS_DV
RX_CTRL		15S, PD, O

Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode.

Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous signal. When CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode.

RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of RX_CLK.

Unused in SGMII mode

TX_CLK28PD, I, O

Transmit Clock: In MII mode, the transmit clock is a 25MHz output and has constant phase referenced to the reference clock. In RGMII mode, this clock is sourced from the MAC layer to the PHY. A 25MHz clock should be provided (not required to have constant phase to the reference clock unless synchronous RGMII is enabled in Section 7.6.15).

Unused in RMII and SGMII modes

TX_EN
TX_CTRL		29PD, I

Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit clock. TX_EN indicates the presence of valid data inputs on TX_D[3:0]. In RMII mode, transmit enable is presented prior to the rising edge of the reference clock. TX_EN indicates the presence of valid data inputs on TX_D[1:0].

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented prior to the falling edge of TX_CLK.

Unused in SGMII mode

TX_D330PD, I

Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the MAC prior to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to the rising edge of the reference clock. TX_D[3:2] are not used in RMII mode.

TX_M / TX_P: Differential SGMII Data Input. These pins receive data that is transmitted from the MAC to the PHY.

TX_D231

TX_D1
TX_P

32

TX_D0
TX_M

33
TX_ER34PD, I

Transmit Error: In MII mode, this pin indicates a transmit error symbol has been detected within a transmitted packet. TX_ER is received prior to the rising edge of TX_CLK.

Unused in RMII, RGMII and SGMII modes

SERIAL MANAGEMENT INTERFACE
MDC1I

Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz. There is no minimum clock rate.

MDIO36OD, IO

Management Data Input/Output: Bidirectional management data signal that may be sourced by the management station or the PHY. This pin requires a pullup resistor.

Recommended to use a resistor between 2.2kΩ and 9kΩ.

CONTROL INTERFACE
INT2PU, OD, O

Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set, register access is required to clear the interrupt event.

Note: Power-on-RESET (POR) Done interrupt is enabled by default. POR Done interrupt can be cleared by reading register Section 7.6.16.

This pin can be configured as an Active-HIGH output using register Section 7.6.9.

RESET3PU, I

Reset: Active-LOW input, which initializes or reinitializes the DP83TC811-Q1. Asserting this pin LOW for at least 1μs will force a reset process to occur. All internal registers will reinitialize to their default states as specified for each bit in the Section 7.6 section. All bootstrap pins are resampled upon deassertion of reset.

EN7PD, I

Enable: Active-HIGH input, which will disable the DP83TC811-Q1 when pulled LOW and power down all internal blocks. Disable state is equivalent to a power-down state.

This pin can be directly tied to VDDIO; enabling the device.

WAKE8PD, I

WAKE: Active-HIGH input, which wakes the PHY from SLEEP. Asserting this pin HIGH at power-up will prevent the PHY from going to SLEEP.

This pin can be directly tied to VDDIO to wake the device.

INH10O

INH: Active-HIGH output, which will be asserted HIGH when the PHY is in SLEEP or DISABLED. This pin is LOW for all other PHY states.

CLOCK INTERFACE
XI5I

Reference Clock Input (MII / RGMII / SGMII): Reference clock 25MHz crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating.

Reference Clock Input (RMII): Reference clock 50MHz CMOS-level oscillator in RMII Slave mode. Reference clock 25MHz crystal or oscillator in RMII Master mode.

This is a fail-safe pin. When the PHY is not powered, an external oscillator is allowed to be powered and driving into this pin. Fail-safe prevents pin back-driving.

XO4O

Reference Clock Output: XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI.

LED/GPIO INTERFACE
LED_0 / GPIO_035S, PD, IO

LED_0: Link Status

LED_1 / GPIO_16S, PD, IO

LED_1: Link Status and BLINK for TX/RX Activity

CLKOUT / GPIO_216IO

Clock Output: 25MHz reference clock

MEDIUM DEPENDENT INTERFACE
TRD_M13IO

Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE 802.3bw compliant.

TRD_P12
JTAG (IEEE 1149.1)
TCK17PU, I

Test Clock: Primary clock source for all test logic input and output. This pin is controlled by the testing entity.

This pin can be left unconnected if not used.

TDO18O

Test Data Output: Test results are scanned out.

This pin can be left unconnected if not used.

TMS19PU, I

Test Mode Select: Sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends applying three clock cycles with TMS HIGH to reset JTAG.

This pin can be left unconnected if not used.

TDI20PU, I

Test Data Input: Test data is scanned into the device.

This pin can be left unconnected if not used.

POWER CONNECTIONS
VDDA11SUPPLY

Core Supply: 3.3V

Recommend using 10nF, 100nF, 1µF, and 10µF ceramic decoupling capacitors; optional ferrite bead.

VDDIO22SUPPLY

IO Supply: 1.8V, 2.5V, 3.3V

Recommend using 10nF, 100nF, 1µF, and 10µF ceramic decoupling capacitors; optional ferrite bead.

GROUNDDAPGROUND

Ground

DO NOT CONNECT
DNC9

DNC: Do not connect (leave floating)

DNC21

DNC: Do not connect (leave floating)

(1) Pin Type:
I = Input
O = Output
IO = Input/Output
OD = Open Drain
PD = Internal pulldown
PU = Internal pullup
S = Bootstrap configuration pin (all configuration pins have weak internal pullups or pulldowns)
(2) When pins are unused, follow the recommended connection requirements provided in the table above. If pins do not have required termination, they may be left floating.
Table 5-2 Pin States(1)
PIN
NAME		POWER-UP / RESETNORMAL OPERATION: MII / RMII / RGMII / SGMII
PIN STATEPULL TYPEPULL VALUE
(kΩ)		PIN STATEPULL TYPEPULL VALUE
(kΩ)
MDCInonenoneInonenone
INTIPU9OD, OPU9
RESETIPU9IPU9
XOOnonenoneOnonenone
XIInonenoneInonenone
LED_1HI-ZPD9Ononenone
ENIPD500IPD500
WAKEIPD500IPD500
DNCFLOATnonenoneFLOATnonenone
INHOnonenoneOnonenone
VDDASUPPLYnonenoneSUPPLYnonenone
TRD_PIOnonenoneIOnonenone
TRD_MIOnonenoneIOnonenone
RX_ERHI-ZPD9Ononenone
RX_DVHI-ZPD9Ononenone
CLKOUTOnonenoneOnonenone
TCKIPU9IPU9
TDOOnonenoneOnonenone
TMSIPU9IPU9
TDIIPU9IPU9
DNCFLOATnonenoneFLOATnonenone
VDDIOSUPPLYnonenoneSUPPLYnonenone
RX_D3HI-ZPD9Ononenone
RX_D2HI-ZPD9Ononenone
RX_D1HI-ZPD9Ononenone
RX_D0HI-ZPD9Ononenone
RX_CLKOnonenoneOnonenone
TX_CLKIPD9O
I(2)		none
PD(2)		none
9(2)
TX_ENIPD9IPD9
TX_D3IPD9IPD9
TX_D2IPD9IPD9
TX_D1IPD9IPD9
TX_D0IPD9IPD9
TX_ERIPD9IPD9
LED_0HI-ZPD9Ononenone
MDIOOD, IOnonenoneOD, IOnonenone
(1) Type: I = Input
O = Output
IO = Input/Output
OD = Open Drain
PD = Internal pulldown
PU = Internal pullup
(2) Pin operation only for RGMII operation.