SNLS579 Data sheet

SNLS579A April 2018 – November 2018 DP83TC811S-Q1

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RND|36
- MPQF428

Thermal pad, mechanical data (Package|Pins)

Orderable Information

snls579a_oa

6 Pin Configuration and Functions

RND Package

36-Pin VQFN

Top View

DP83TC811S-Q1 pin_map_DP83TC811_SGMII_snls551.gif

Pin Functions⁽²⁾

PIN		STATE⁽¹⁾	DESCRIPTION
NAME	NO.	STATE⁽¹⁾	DESCRIPTION
MAC INTERFACE
RX_D 3 RX_M	23	S, PD, O	Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A data nibble, RX_D[3:0], is transmitted in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII mode. RX_D[3:2] are not used when in RMII mode. If the PHY is bootstrapped to RMII Master mode, a 50-MHz clock reference is automatically outputted on RX_D3. This clock should be fed to the MAC. RX_M / RX_P: Differential SGMII Data Output. These pins transmit data from the PHY to the MAC. This data is synchronous to the differential SGMII clock output. RXCLK_M / RXCLK_P: Differential SGMII Clock Output. This signal is a continuous 625-MHz clock signal driven by the PHY in 6-wire SGMII mode. (configurable through register access)
RX_D2 RX_P	24
RX_D1 RXCLK_M	25
RX_D0 RXCLK_P	26
RX_CLK	27	O	Receive Clock: In MII and RGMII modes, the receive clock provides a 25-MHz reference clock. Unused in RMII and SGMII modes
RX_ER	14	S, PD, O	Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected within a received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required to be used by the MAC in MII or RMII because the PHY will automatically corrupt data on a receive error. Unused in RGMII and SGMII modes
RX_DV CRS_DV RX_CTRL	15	S, PD, O	Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode. Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous signal. When CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode. RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of RX_CLK. Unused in SGMII mode
TX_CLK	28	PD, I, O	Transmit Clock: In MII mode, the transmit clock is a 25-MHz output and has constant phase referenced to the reference clock. In RGMII mode, this clock is sourced from the MAC layer to the PHY. A 25-MHz clock should be provided (not required to have constant phase to the reference clock unless synchronous RGMII is enabled in xMII_CTRL Register 0x0017 – xMII Control Register). Unused in RMII and SGMII modes
TX_EN TX_CTRL	29	PD, I	Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit clock. TX_EN indicates the presence of valid data inputs on TX_D[3:0]. In RMII mode, transmit enable is presented prior to the rising edge of the reference clock. TX_EN indicates the presence of valid data inputs on TX_D[1:0]. RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented prior to the falling edge of TX_CLK. Unused in SGMII mode
TX_D3	30	PD, I	Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the MAC prior to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to the rising edge of the reference clock. TX_D[3:2] are not used in RMII mode. TX_M / TX_P: Differential SGMII Data Input. These pins receive data that is transmitted from the MAC to the PHY.
TX_D2	31
TX_D1 TX_P	32
TX_D0 TX_M	33
TX_ER	34	PD, I	Transmit Error: In MII mode, this pin indicates a transmit error symbol has been detected within a transmitted packet. TX_ER is received prior to the rising edge of TX_CLK. Unused in RMII, RGMII and SGMII modes
SERIAL MANAGEMENT INTERFACE
MDC	1	I	Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.
MDIO	36	OD, IO	Management Data Input/Output: Bidirectional management data signal that may be sourced by the management station or the PHY. This pin requires a pullup resistor. Recommended to use a resistor between 2.2 kΩ and 9 kΩ.
CONTROL INTERFACE
INT	2	PU, OD, O	Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set, register access is required to clear the interrupt event. Note: Power-on-RESET (POR) Done interrupt is enabled by default. POR Done interrupt can be cleared by reading register INT_STAT3 Register 0x0018 – Interrupt Status Register #3. This pin can be configured as an Active-HIGH output using register INT_TEST Register 0x0011 – Interrupt Test Register.
RESET	3	PU, I	Reset: Active-LOW input, which initializes or reinitializes the DP83TC811S-Q1. Asserting this pin LOW for at least 1 μs will force a reset process to occur. All internal registers will reinitialize to their default states as specified for each bit in the Register Maps section. All bootstrap pins are resampled upon deassertion of reset.
EN	7	PD, I	Enable: Active-HIGH input, which will disable the DP83TC811S-Q1 when pulled LOW and power down all internal blocks. Disable state is equivalent to a power-down state. This pin can be directly tied to VDDIO; enabling the device.
WAKE	8	PD, I	WAKE: Active-HIGH input, which wakes the PHY from SLEEP. Asserting this pin HIGH at power-up will prevent the PHY from going to SLEEP. This pin can be directly tied to VDDIO to wake the device.
INH	10	O	INH: Active-HIGH output, which will be asserted HIGH when the PHY is in SLEEP or DISABLED. This pin is LOW for all other PHY states.
CLOCK INTERFACE
XI	5	I	Reference Clock Input (MII / RGMII / SGMII): Reference clock 25-MHz crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating. Reference Clock Input (RMII): Reference clock 50-MHz CMOS-level oscillator in RMII Slave mode. Reference clock 25-MHz crystal or oscillator in RMII Master mode. This is a fail-safe pin. When the PHY is not powered, an external oscillator is allowed to be powered and driving into this pin. Fail-safe prevents pin back-driving.
XO	4	O	Reference Clock Output: XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI.
LED/GPIO INTERFACE
LED_0 / GPIO_0	35	S, PD, IO	LED_0: Link Status
LED_1 / GPIO_1	6	S, PD, IO	LED_1: Link Status and BLINK for TX/RX Activity
CLKOUT / GPIO_2	16	IO	Clock Output: 25-MHz reference clock
MEDIUM DEPENDENT INTERFACE
TRD_M	13	IO	Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE 802.3bw compliant.
TRD_P	12	IO
JTAG (IEEE 1149.1)
TCK	17	PU, I	Test Clock: Primary clock source for all test logic input and output. This pin is controlled by the testing entity. This pin can be left unconnected if not used.
TDO	18	O	Test Data Output: Test results are scanned out. This pin can be left unconnected if not used.
TMS	19	PU, I	Test Mode Select: Sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends applying three clock cycles with TMS HIGH to reset JTAG. This pin can be left unconnected if not used.
TDI	20	PU, I	Test Data Input: Test data is scanned into the device. This pin can be left unconnected if not used.
POWER CONNECTIONS
VDDA	11	SUPPLY	Core Supply: 3.3 V Recommend using 10-nF, 100-nF, 1-µF, and 10-µF ceramic decoupling capacitors; optional ferrite bead.
VDDIO	22	SUPPLY	IO Supply: 1.8 V, 2.5 V, or 3.3 V Recommend using 10-nF, 100-nF, 1-µF, and 10-µF ceramic decoupling capacitors; optional ferrite bead.
GROUND	DAP	GROUND	Ground
DO NOT CONNECT
DNC	9		DNC: Do not connect (leave floating)
DNC	21		DNC: Do not connect (leave floating)

(1) Pin Type:
I = Input
O = Output
IO = Input/Output
OD = Open Drain
PD = Internal pulldown
PU = Internal pullup
S = Bootstrap configuration pin (all configuration pins have weak internal pullups or pulldowns)

(2) When pins are unused, follow the recommended connection requirements provided in the table above. If pins do not have required termination, they may be left floating.

Table 1. Pin States⁽¹⁾

PIN NAME	POWER-UP / RESET			NORMAL OPERATION: MII / RMII / RGMII / SGMII
PIN NAME	PIN STATE	PULL TYPE	PULL VALUE (kΩ)	PIN STATE	PULL TYPE	PULL VALUE (kΩ)
MDC	I	none	none	I	none	none
INT	I	PU	9	OD, O	PU	9
RESET	I	PU	9	I	PU	9
XO	O	none	none	O	none	none
XI	I	none	none	I	none	none
LED_1	HI-Z	PD	9	O	none	none
EN	I	PD	500	I	PD	500
WAKE	I	PD	500	I	PD	500
DNC	FLOAT	none	none	FLOAT	none	none
INH	O	none	none	O	none	none
VDDA	SUPPLY	none	none	SUPPLY	none	none
TRD_P	IO	none	none	IO	none	none
TRD_M	IO	none	none	IO	none	none
RX_ER	HI-Z	PD	9	O	none	none
RX_DV	HI-Z	PD	9	O	none	none
CLKOUT	O	none	none	O	none	none
TCK	I	PU	9	I	PU	9
TDO	O	none	none	O	none	none
TMS	I	PU	9	I	PU	9
TDI	I	PU	9	I	PU	9
DNC	FLOAT	none	none	FLOAT	none	none
VDDIO	SUPPLY	none	none	SUPPLY	none	none
RX_D3	HI-Z	PD	9	O	none	none
RX_D2	HI-Z	PD	9	O	none	none
RX_D1	HI-Z	PD	9	O	none	none
RX_D0	HI-Z	PD	9	O	none	none
RX_CLK	O	none	none	O	none	none
TX_CLK	I	PD	9	O I⁽²⁾	none PD⁽²⁾	none 9⁽²⁾
TX_EN	I	PD	9	I	PD	9
TX_D3	I	PD	9	I	PD	9
TX_D2	I	PD	9	I	PD	9
TX_D1	I	PD	9	I	PD	9
TX_D0	I	PD	9	I	PD	9
TX_ER	I	PD	9	I	PD	9
LED_0	HI-Z	PD	9	O	none	none
MDIO	OD, IO	none	none	OD, IO	none	none

(1) Type: I = Input
O = Output
IO = Input/Output
OD = Open Drain
PD = Internal pulldown
PU = Internal pullup

(2) Pin operation only for RGMII operation.