SNLS579 Data sheet

SNLS579A April 2018 – November 2018 DP83TC811S-Q1

PRODUCTION DATA.

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8.4.13.2 Reduced Media Independent Interface

The DP83TC811S-Q1 incorporates the Reduced Media Independent Interface (RMII) as defined in the RMII Revision 1.2 and 1.0 from the RMII consortium. The purpose of this interface is to provide a reduced pin count alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII.

The DP83TC811S-Q1 offers two types of RMII operations: RMII Slave and RMII Master. In RMII Slave Mode, the DP83TC811S-Q1 operates off a 50-MHz CMOS-level oscillator, which is either provided by the MAC or synchronous to the MAC's reference clock. In RMII Master operation, the DP83TC811S-Q1 operates off of either a 25-MHz CMOS-level oscillator connected to XI pin or a 25-MHz crystal connected across XI and XO pins. When bootstrapping to RMII Master Mode, a 50-MHz output clock will automatically be enabled on RX_D3. This 50-MHz output clock should be routed to the MAC.

The RMII specification has the following characteristics:

Single clock reference shared between MAC and PHY
Provides independent 2-bit wide transmit and receive data paths

In this mode, data transfers are two bits for every clock cycle using the 50-MHz reference clock for both transmit and receive paths.

The RMII signals are summarized in Table 8:

Table 8. RMII Signals

FUNCTION	PINS
Data Signals	TX_D[1:0]
Data Signals	RX_D[1:0]
Control Signals	TX_EN
Control Signals	CRS_DV

DP83TC811S-Q1 RMII_connection_snls551.gif

Figure 25. RMII Signaling

Table 9. RMII Transmit Encoding

TX_EN	TX_D[1:0]	DESCRIPTION
0	00 through 11	Normal Inter-Frame
1	00 through 11	Normal Data Transmission

Table 10. RMII Receive Encoding

CRS_DV	RX_ER	RX_D[1:0]	DESCRIPTION
0	0	00 through 11	Normal Inter-Frame
0	1	00	Normal Inter-Frame
0	1	01 through 11	Reserved
1	0	00 through 11	Normal Data Reception
1	1	00 through 11	Data Reception with Errors

RMII Slave: Data on TX_D[1:0] are latched at the PHY with reference to the rising edge of the reference clock at the XI pin. Data is presented on RX_D[1:0] with reference to the same rising clock edges at the XI pin.

RMII Master: Data on TX_D[1:0] are latched at the PHY with reference to the rising edge of the reference clock at the RX_D3 pin. Data is presented on RX_D[1:0] with reference to the same rising clock edges at the RX_D3 pin.

The DP83TC811S-Q1 RMII supplies an RX_DV signal, which provides a simpler method to recover receive data without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though it is not required by the RMII specification.

RMII includes a programmable FIFO to adjust for the frequency differences between the reference clock and the recovered clock. The programmable FIFO, located in the xMII_CTRL Register 0x0017 – xMII Control Register, minimizes internal propagation delay based on expected maximum packet size and clock accuracy.

Table 11 indicates how to program the FIFO based on the expected maximum packet size and clock accuracy. This table is based on the assumption that the local reference clock and link partner reference clock have the same accuracy.

Table 11. Recommended RMII Packet Sizes

START THRESHOLD	RECOMMENDED PACKET SIZE AT ±100ppm
2-bits	1250 bytes
3-bits	3750 bytes
4-bits	6250 bytes
5-bits	8750 bytes