SNLS654C April   2021  – November 2024 DP83TC812R-Q1 , DP83TC812S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Electrostatic Discharge Sensing
        3. 7.3.1.3 Time Domain Reflectometry
        4. 7.3.1.4 Voltage Sensing
        5. 7.3.1.5 BIST and Loopback Modes
          1. 7.3.1.5.1 Data Generator and Checker
          2. 7.3.1.5.2 xMII Loopback
          3. 7.3.1.5.3 PCS Loopback
          4. 7.3.1.5.4 Digital Loopback
          5. 7.3.1.5.5 Analog Loopback
          6. 7.3.1.5.6 Reverse Loopback
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Down
      2. 7.4.2  Reset
      3. 7.4.3  Standby
      4. 7.4.4  Normal
      5. 7.4.5  Sleep Ack
      6. 7.4.6  Sleep Request
      7. 7.4.7  Sleep Fail
      8. 7.4.8  Sleep
      9. 7.4.9  Wake-Up
      10. 7.4.10 TC10 System Example
      11. 7.4.11 Media Dependent Interface
        1. 7.4.11.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 7.4.11.2 Auto-Polarity Detection and Correction
        3. 7.4.11.3 Jabber Detection
        4. 7.4.11.4 Interleave Detection
      12. 7.4.12 MAC Interfaces
        1. 7.4.12.1 Media Independent Interface
        2. 7.4.12.2 Reduced Media Independent Interface
        3. 7.4.12.3 Reduced Gigabit Media Independent Interface
        4. 7.4.12.4 Serial Gigabit Media Independent Interface
      13. 7.4.13 Serial Management Interface
        1. 7.4.13.1 Direct Register Access
        2. 7.4.13.2 Extended Register Space Access
        3. 7.4.13.3 Write Operation (No Post Increment)
        4. 7.4.13.4 Read Operation (No Post Increment)
        5. 7.4.13.5 Write Operation (Post Increment)
        6. 7.4.13.6 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Register Access Summary
      2. 7.6.2 DP83TC812 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information Disclaimer
    2. 8.2 Application Information
    3. 8.3 Typical Applications
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Physical Medium Attachment
          1. 8.3.1.1.1 Common-Mode Choke Recommendations
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Signal Traces
        2. 8.5.1.2 Return Path
        3. 8.5.1.3 Metal Pour
        4. 8.5.1.4 PCB Layer Stacking
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Revision History

Changes from Revision B (January 2023) to Revision C (November 2024)

  • Updated Pin 9 and Pin 21 pin descriptions and package labelGo
  • Table 5-1 Pin Functions: Updated MDIO pin description to include link to Compliance Test Modes sectionGo
  • Table 6-1 Pin Functions: Updated description for RX_D3 for SGMII modeGo
  • Table 6-1 Pin Functions: Updated Pin 15 description to include register writes for programming Pin 15 as RX_DV and CRS_DVGo
  • Table 6-1 Pin Functions: Clarified that RX_D3 and RX_D2 are not used in RMII Slave modeGo
  • Removed RGMII Timing Diagrams for Internal Delay Enabled and Internal Delay Disabled modes and created a new RGMII Transmit Timing Diagram for clarityGo
  • Corrected description for register 0x310 Bit 6Go
  • Corrected order of register writes for enabling data generator/checkerGo
  • Corrected RGMII Transmit Encoding table for Normal Data Transmission and Transmit Error Propogation Go
  • Updated Serial Management Interface section with better wording and clarityGo
  • Table 7-25. PHY Address Bootstraps: Corrected binary representations of PHY addresses 0xC and 0xDGo
  • Register 0x18, Bit 15 has been removedGo
  • Register 0x60B has been removedGo
  • Register 0x609 has been removedGo
  • Register 0x603 has been removedGo
  • Register 0x456, clarified Bit DescriptionGo
  • Register 0x12, Bit 7 has been removedGo
  • Register 0x1F, clarified Bit 15 and Bit 14 DescriptionGo
  • Added general typical application diagramGo
  • Updated RGMII Typical Application diagram to include 25MHz inputGo
  • Simplified and updated the Detailed Design Procedure and added a link to the Schematic ChecklistGo

Changes from Revision A (December 2021) to Revision B (January 2023)

  • Added 'Functional Safety-Capable' to Feature ListGo
  • Table 6-1 Pin Functions: Changed TX_CLK description to include (50 ohm Driver) for MII transmit clock.Go
  • Table 6-4 Pin States -TC10 SLEEP: Changed the PULL TYPE of Pin 16 CLKOUT from PD->noneGo
  • Added line to CLKOUT/GPIO2's description about which registers to program to disable switchingGo
  • Added line to INT pin description. Reg 12-13 is recommended to be read only when INT_N is LOWGo
  • MDC clock rate changed from 25MHz->20MHz in Serial Management Interface Section of Pin Function TableGo
  • Updated Iozh to clarify mapping of Rx_Ctrl and Rx_ER pinsGo
  • Removed Supply ramp delay offset: For all suppliesGo
  • Power-Up Timing figure correctedGo
  • PHY Operation State Diagram figure updatedGo
  • Added Auto-clear note to register 0x18B[6]Go
  • Added XI clock PPM TableGo
  • Added Auto-clear note to register 0x18B[6]Go
  • Register 0x63E, clarified Bit DescriptionGo
  • Register 0x63D, clarified Bit DescriptionGo
  • Register 0x63C, clarified Bit DescriptionGo
  • Register 0x63B, clarified Bit DescriptionGo
  • Register 0x63A, clarified Bit DescriptionGo
  • Register 0x639, clarified Bit DescriptionGo
  • Register 0x451, clarified Bit Descriptions Go
  • Register 0x18B has been addedGo
  • Register 0x12, Bit 15 has been removedGo

Changes from Revision * (April 2021) to Revision A (December 2021)

  • Advance Information to Production Data ReleaseGo