SNLS654C April   2021  – November 2024 DP83TC812R-Q1 , DP83TC812S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Electrostatic Discharge Sensing
        3. 7.3.1.3 Time Domain Reflectometry
        4. 7.3.1.4 Voltage Sensing
        5. 7.3.1.5 BIST and Loopback Modes
          1. 7.3.1.5.1 Data Generator and Checker
          2. 7.3.1.5.2 xMII Loopback
          3. 7.3.1.5.3 PCS Loopback
          4. 7.3.1.5.4 Digital Loopback
          5. 7.3.1.5.5 Analog Loopback
          6. 7.3.1.5.6 Reverse Loopback
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Down
      2. 7.4.2  Reset
      3. 7.4.3  Standby
      4. 7.4.4  Normal
      5. 7.4.5  Sleep Ack
      6. 7.4.6  Sleep Request
      7. 7.4.7  Sleep Fail
      8. 7.4.8  Sleep
      9. 7.4.9  Wake-Up
      10. 7.4.10 TC10 System Example
      11. 7.4.11 Media Dependent Interface
        1. 7.4.11.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 7.4.11.2 Auto-Polarity Detection and Correction
        3. 7.4.11.3 Jabber Detection
        4. 7.4.11.4 Interleave Detection
      12. 7.4.12 MAC Interfaces
        1. 7.4.12.1 Media Independent Interface
        2. 7.4.12.2 Reduced Media Independent Interface
        3. 7.4.12.3 Reduced Gigabit Media Independent Interface
        4. 7.4.12.4 Serial Gigabit Media Independent Interface
      13. 7.4.13 Serial Management Interface
        1. 7.4.13.1 Direct Register Access
        2. 7.4.13.2 Extended Register Space Access
        3. 7.4.13.3 Write Operation (No Post Increment)
        4. 7.4.13.4 Read Operation (No Post Increment)
        5. 7.4.13.5 Write Operation (Post Increment)
        6. 7.4.13.6 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Register Access Summary
      2. 7.6.2 DP83TC812 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information Disclaimer
    2. 8.2 Application Information
    3. 8.3 Typical Applications
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Physical Medium Attachment
          1. 8.3.1.1.1 Common-Mode Choke Recommendations
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Signal Traces
        2. 8.5.1.2 Return Path
        3. 8.5.1.3 Metal Pour
        4. 8.5.1.4 PCB Layer Stacking
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
100BASE-T1 PMA CONFORMANCE
VOD-MDI Output Differential Voltage RL(diff) = 100Ω 2.2 V
RMDI-Diff Integrated Differential Output Termination TRD_P and TRD_M 100 Ω
BOOTSTRAP DC CHARACTERISTICS (2 Level)
VMODE1 Mode 1 Strap Voltage Range  VDDIO = 3.3V ±10%, 2-level strap 0 0.8 V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 3.3V ±10%, 2-level strap 2 VDDIO V
VMODE1 Mode 1 Strap Voltage Range  VDDIO = 2.5V ±10%, 2-level strap 0 0.7 V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 2.5V ±10%, 2-level strap 1.5 VDDIO V
VMODE1 Mode 1 Strap Voltage Range  VDDIO = 1.8V ±10%, 2-level strap 0 0.35 x VDDIO V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 1.8V ±10%, 2-level strap 0.65 x VDDIO VDDIO V
BOOTSTRAP DC CHARACTERISTICS (3 Level)
VMODE1 Mode 1 Strap Voltage Range VDDIO = 3.3V ±10%, 3-level strap 0 0.18 x VDDIO V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 3.3V ±10%, 3-level strap 0.22 x VDDIO 0.42 x VDDIO V
VMODE3 Mode 3 Strap Voltage Range VDDIO = 3.3V ±10%, 3-level strap 0.46 x VDDIO  VDDIO V
VMODE1 Mode 1 Strap Voltage Range VDDIO = 2.5V ±10%, 3-level strap 0 0.19 x VDDIO V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 2.5V ±10%, 3-level strap 0.27 x VDDIO 0.41 x VDDIO V
VMODE3 Mode 3 Strap Voltage Range VDDIO = 2.5V ±10%, 3-level strap 0.58 x VDDIO  VDDIO V
VMODE1 Mode 1 Strap Voltage Range VDDIO = 1.8V ±10%, 3-level strap 0 0.35 x VDDIO V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 1.8V ±10%, 3-level strap 0.40 x VDDIO 0.75 x VDDIO V
VMODE3 Mode 3 Strap Voltage Range VDDIO = 1.8V ±10%, 3-level strap 0.84 x VDDIO  VDDIO V
IO CHARACTERISTICS
VIH High Level Input Voltage VDDIO = 3.3V ±10% 2 V
VIL Low Level Input Voltage VDDIO = 3.3V ±10% 0.8 V
VOH High Level Output Voltage IOH = -2mA, VDDIO = 3.3V ±10% 2.4 V
VOL Low Level Output Voltage IOL = 2mA, VDDIO = 3.3V ±10% 0.4 V
VIH High Level Input Voltage VDDIO = 2.5V ±10% 1.7 V
VIL Low Level Input Voltage VDDIO = 2.5V ±10% 0.7 V
VOH High Level Output Voltage IOH = -2mA, VDDIO = 2.5V ±10% 2 V
VOL Low Level Output Voltage IOL = 2mA, VDDIO = 2.5V ±10% 0.4 V
VIH High Level Input Voltage VDDIO = 1.8V ±10% 0.65*VDDIO V
VIL Low Level Input Voltage VDDIO = 1.8V ±10% 0.35*VDDIO V
VOH High Level Output Voltage IOH = -2mA, VDDIO = 1.8V ±10% VDDIO-0.45 V
VOL Low Level Output Voltage IOL = 2mA, VDDIO = 1.8V ±10% 0.45 V
IIH Input High Current(1) TA = -40℃ to 125℃, VIN=VDDIO, All pins except XI and WAKE -10 10 µA
IIH-XI Input High Current(2) TA = -40℃ to 125℃, VIN=VDDIO, XI pin -15 15 µA
IIL-XI Input Low Current(1) TA = -40℃ to 125℃, VIN=GND, XI pin -15 15 µA
IIL Input Low Current(1) TA = -40℃ to 125℃, VIN=GND, All pins except XI pin -10 10 µA
Iozh Tri-state Output High Current TA = -40℃ to 125℃, VIN=VDDIO, For pins RX_D[3:0], RX_CLK, MDIO, INT_N and XO -10 10 µA
Iozh Tri-state Output High Current TA = -40℃ to 125℃, VIN=VDDIO, For pins RX_CTRL and RX_ER -52 52 µA
Iozl Tri-state Output Low Current(2) TA = -40℃ to 125℃, VOUT=GND -10 10 µA
Rpulldn Internal Pull Down Resistor RX_D[3:0], RX_CLK, LED_0, LED_1 6.2 8.4 10.7 kΩ
Rpulldn Internal Pull Down Resistor RX_CTRL, RX_ER 4.725 5.8 7.2 kΩ
Rpulldn Internal Pull Down Resistor WAKE 455 kΩ
Rpullup Internal Pull Up Resistor INT, RESET 6.3 9 11.2 kΩ
XI VIH High Level Input Voltage 1.3 VDDIO V
XI VIL Low Level Input Voltage 0.5 V
CIN Input Capacitance XI 1 pF
CIN Input Capacitance INPUT PINS 5 pF
COUT Output Capacitance XO 1 pF
COUT Output Capacitance OUTPUT PINS 5 pF
Rseries Integrated MAC Series Termination Resistor RX_D[3:0], RX_ER, RX_DV, RX_CLK 35 50 65 Ω
POWER CONSUMPTION
I(3V3) MII -40℃ to 125℃ 57 63 mA
I(3V3) RMII -40℃ to 125℃ 57 63 mA
I(3V3) RGMII -40℃ to 125℃ 57 63 mA
I(3V3) SGMII -40℃ to 125℃ 81 95 mA
I(VDDIO=3.3V) MII -40℃ to 125℃, VDDIO = VDDMAC 19 24 mA
I(VDDIO=3.3V) RMII -40℃ to 125℃, VDDIO = VDDMAC 18 23 mA
I(VDDIO=3.3V) RGMII -40℃ to 125℃, VDDIO = VDDMAC 13 21 mA
I(VDDIO=3.3V) SGMII -40℃ to 125℃, VDDIO = VDDMAC 7 12 mA
I(VDDIO=2.5V) MII -40℃ to 125℃, VDDIO = VDDMAC 12 18 mA
I(VDDIO=2.5V) RMII -40℃ to 125℃, VDDIO = VDDMAC 12 17 mA
I(VDDIO=2.5V) RGMII -40℃ to 125℃, VDDIO = VDDMAC 12 16 mA
I(VDDIO=2.5V) SGMII -40℃ to 125℃, VDDIO = VDDMAC 6 9 mA
I(VDDIO=1.8V) MII -40℃ to 125℃, VDDIO = VDDMAC 9 13 mA
I(VDDIO=1.8V) RMII -40℃ to 125℃, VDDIO = VDDMAC 9 13 mA
I(VDDIO=1.8V) RGMII -40℃ to 125℃, VDDIO = VDDMAC 9 12 mA
I(VDDIO=1.8V) SGMII -40℃ to 125℃, VDDIO = VDDMAC 4 6 mA
POWER CONSUMPTION (LOW POWER MODE)
I(VDDA3V3) IEEE Power Down -40℃ to 125℃, All interfaces 8 22 mA
I(VDDA3V3) TC-10 Sleep -40℃ to 125℃, All interfaces 30 50 mA
I(VDDA3V3) RESET -40℃ to 125℃, All interfaces 9 23 mA
I(VDDA3V3) Standby -40℃ to 125℃, MII 15 33 mA
I(VDDA3V3) Standby -40℃ to 125℃, RMII 15 30 mA
I(VDDA3V3) Standby -40℃ to 125℃, RGMII 15 30 mA
I(VDDA3V3) Standby -40℃ to 125℃, SGMII 15 30 mA
I(VDDIO=3.3V) IEEE Power Down -40℃ to 125℃, All interfaces, VDDIO=VDDMAC 15 23 mA
I(VDDIO=3.3V) TC-10 Sleep -40℃ to 125℃, All interfaces, VDDIO=VDDMAC 15 23 mA
I(VDDIO=3.3V) RESET -40℃ to 125℃, All interfaces, VDDIO=VDDMAC 15 23 mA
I(VDDIO=3.3V) Standby -40℃ to 125℃, MII, VDDIO=VDDMAC 19 25 mA
I(VDDIO=3.3V) Standby -40℃ to 125℃, RMII, VDDIO=VDDMAC 16 20 mA
I(VDDIO=3.3V) Standby -40℃ to 125℃, RGMII, VDDIO=VDDMAC 14 20 mA
I(VDDIO=3.3V) Standby -40℃ to 125℃, SGMII, VDDIO=VDDMAC 14 16 mA
I(VDDIO=2.5V) IEEE Power Down -40℃ to 125℃, All interfaces, VDDIO=VDDMAC 10 16 mA
I(VDDIO=2.5V) TC-10 Sleep -40℃ to 125℃, All interfaces, VDDIO=VDDMAC 10 16 mA
I(VDDIO=2.5V) RESET -40℃ to 125℃, All interfaces, VDDIO=VDDMAC 10 16 mA
I(VDDIO=2.5V) Standby -40℃ to 125℃, MII, VDDIO=VDDMAC 14 18 mA
I(VDDIO=2.5V) Standby -40℃ to 125℃, RMII, VDDIO=VDDMAC 11 14 mA
I(VDDIO=2.5V) Standby -40℃ to 125℃, RGMII, VDDIO=VDDMAC 9 14 mA
I(VDDIO=2.5V) Standby -40℃ to 125℃, SGMII, VDDIO=VDDMAC 9 14 mA
I(VDDIO=1.8V) IEEE Power Down -40℃ to 125℃, All interfaces, VDDIO=VDDMAC 7 11 mA
I(VDDIO=1.8V) TC-10 Sleep -40℃ to 125℃, All interfaces, VDDIO=VDDMAC 7 11 mA
I(VDDIO=1.8V) RESET -40℃ to 125℃, All interfaces, VDDIO=VDDMAC 7 11 mA
I(VDDIO=1.8V) Standby -40℃ to 125℃, MII, VDDIO=VDDMAC 10 12 mA
I(VDDIO=1.8V) Standby -40℃ to 125℃, RMII, VDDIO=VDDMAC 7 11 mA
I(VDDIO=1.8V) Standby -40℃ to 125℃, RGMII, VDDIO=VDDMAC 6 11 mA
I(VDDIO=1.8V) Standby -40℃ to 125℃, SGMII, VDDIO=VDDMAC 6 11 mA
I(VSLEEP) TC-10 Sleep -40℃ to 125℃, All interfaces, All other supplies are off 7 18 µA
SGMII Input
VIDTH Input differential voltage tolerance SI_P and SI_N, AC coupled 0.1 V
RIN-DIFF Receiver differential input impedance (DC) 80 120 ohm
SGMII Output
Clock signal duty cycle SO_P and SO_N, AC coupled, 0101010101 pattern 48 52 %
Output Differential Voltage SO_P and SO_N, AC coupled 150 400 mV
Voltage Sensor
VDDA VDDA  Sensor Range -40℃ to +125℃ 2.7 3.3 4 V
VDDA Sensor Resolution (LSB) -40℃ to +125℃ 8.8 mV
VDDA Sensor Accuracy (voltage and temperature variation on single part) -40℃ to +125℃ -120 120 mV
VDDA Sensor Accuracy (part-part variation) -40℃ to +125℃ -50 50 mV
VDDIO / VDDMAC VDDIO / VDDMAC  Sensor Range -40℃ to +125℃ 1.44 3.9 V
VDDIO / VDDMAC Sensor Resolution (LSB) -40℃ to +125℃ 16 mV
VDDIO / VDDMAC Sensor Accuracy (voltage and temperature variation on single part) -40℃ to +125℃ -144 144 mV
VDDIO / VDDMAC Sensor Accuracy (part-part variation) -40℃ to +125℃ -85 85 mV
VSLEEP VSLEEP Sensor Range -40℃ to +125℃ 2.7 3.3 4 V
VSLEEP Sensor Resolution (LSB) -40℃ to +125℃ 8.8 mV
VSLEEP Sensor Accuracy (voltage and temperature variation on single part) -40℃ to +125℃ -120 120 mV
VSLEEP Sensor Accuracy (part-part variation) -40℃ to +125℃ -50 50 mV
(1) For pins: MDC, TX_CLK, TX_CTRL, TX_D[3:0], and RESET_N
(2) For pins: RX_D[3:0], RX_CLK, RX_CTRL, MDIO, INT_N, and XO.