6 Pin Configuration and Functions

RX_D3
RX_M

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A data nibble, RX_D[3:0], is transmitted in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII mode. RX_D[3:2] are not used when in RMII mode.

If the PHY is bootstrapped to RMII Master mode, a 50-MHz clock reference is automatically outputted on RX_D3. This clock must be fed to the MAC.

RX_M / RX_P: Differential SGMII Data Output. These pins transmit data from the PHY to the MAC.

RX_D2
RX_P

RX_D1

RX_D0

Receive Clock: In MII and RGMII modes, the receive clock provides a 25-MHz reference clock.

Unused in RMII and SGMII modes

Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected within a received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required to be used by the MAC in MII or RMII because the PHY will automatically corrupt data on a receive error.

Unused in RGMII and SGMII modes

Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode.

Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous signal. When CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode.

RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of RX_CLK.

Unused in SGMII mode

Transmit Clock: In MII mode, the transmit clock is a 25-MHz output and has constant phase referenced to the reference clock. In RGMII mode, this clock is sourced from the MAC layer to the PHY. A 25-MHz clock must be provided (not required to have constant phase to the reference clock unless synchronous RGMII is enabled).

Unused in RMII and SGMII modes

Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit clock. TX_EN indicates the presence of valid data inputs on TX_D[3:0]. In RMII mode, transmit enable is presented prior to the rising edge of the reference clock. TX_EN indicates the presence of valid data inputs on TX_D[1:0].

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented prior to the falling edge of TX_CLK.

Unused in SGMII mode

Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the MAC prior to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to the rising edge of the reference clock. TX_D[3:2] are not used in RMII mode.

TX_M / TX_P: Differential SGMII Data Input. These pins receive data that is transmitted from the MAC to the PHY.

TX_D1
TX_P

TX_D0
TX_M

Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock may be asynchronous to the MAC transmit and receive clocks.

Management Data Input/Output: Bidirectional management data signal that may be sourced by the management station or the PHY. This pin requires a pullup resistor. In systems with multiple PHYs using same MDIO-MDC bus, a single pull-up resistor must be used on MDIO line.

Recommended to use a resistor between 2.2 kΩ and 9 kΩ.

Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set, register access is required to clear the interrupt event. This pin can be configured as an Active-HIGH output using register 0x0011.

This pin can also operate as Power-Down control where asserting this pin low would put the PHY in power down mode and asserting high would put the PHY in normal mode. This feature can also be enabled via register 0x0011.

Reset: Active-LOW input, which initializes or reinitializes the PHY. Asserting this pin LOW for at least 1 μs will force a reset process to occur. All internal registers will reinitialize to their default states as specified for each bit in the Register Maps section. All bootstrap pins are resampled upon deassertion of reset.

WAKE: Active-HIGH input, which wakes the PHY from TC-10 SLEEP. Asserting this pin HIGH at power-up will prevent the PHY from going to SLEEP. External 10kΩ pull down resistor can be used when implementing TC-10 circuit to prevent accidental wake-up. This pin can be directly tied to VSLEEP to wake the device.

INH: Active-HIGH output. This pin will be Hi-Z when the PHY is in TC-10 SLEEP. This pin is HIGH for all other PHY states. External 2kΩ - 10kΩ pull down resistor must be used when implementing TC-10 circuit. If multiple devices are sharing INH pin, then a single pull down resistor must be used.

Reference Clock Input (RMII): Reference clock 50-MHz CMOS-level oscillator in RMII Slave mode. Reference clock 25-MHz crystal or oscillator in RMII Master mode.

Reference Clock Input (Other MAC Interfaces): Reference clock 25-MHz crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating.

Reference Clock Output: XO pin is used for crystal only. This pin must be left floating when a CMOS-level oscillator is connected to XI.

Clock Output: 25-MHz reference clock. This pin can be used as LED or GPIO via register configuration.

Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE 802.3bw compliant.