SNLS656D August   2020  – December 2023 DP83TD510E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Auto-Negotiation (Speed Selection)
      2. 6.3.2  Repeater Mode
      3. 6.3.3  Media Converter
      4. 6.3.4  Clock Output
      5. 6.3.5  Media Independent Interface (MII)
      6. 6.3.6  Reduced Media Independent Interface (RMII)
      7. 6.3.7  RMII Low Power 5-MHz Mode
      8. 6.3.8  RGMII Interface
      9. 6.3.9  Serial Management Interface
      10. 6.3.10 Extended Register Space Access
        1. 6.3.10.1 Read (No Post Increment) Operation
        2. 6.3.10.2 Read (Post Increment) Operation
        3. 6.3.10.3 Write (No Post Increment) Operation
        4. 6.3.10.4 Write (Post Increment) Operation
      11. 6.3.11 Loopback Modes
        1. 6.3.11.1 MII Loopback
        2. 6.3.11.2 PCS Loopback
        3. 6.3.11.3 Digital Loopback
        4. 6.3.11.4 Analog Loopback
        5. 6.3.11.5 Far-End (Reverse) Loopback
      12. 6.3.12 BIST Configurations
      13. 6.3.13 Cable Diagnostics
        1. 6.3.13.1 TDR
        2. 6.3.13.2 Fast Link Down Functionality
    4. 6.4 Device Functional Modes
      1. 6.4.1 Straps Configuration
        1. 6.4.1.1 Straps for PHY Address
    5. 6.5 Programming
    6. 6.6 MMD Register Address Map
    7. 6.7 DP83TD510E Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Termination Circuit
        1. 7.2.1.1 Termination Circuit for Intrinsic Safe Applications
        2. 7.2.1.2 Components Range for Power Coupling/Decoupling
        3. 7.2.1.3 Termination Circuit for Non-Intrinsic Safe Applications
        4. 7.2.1.4 CMC Specifications
      2. 7.2.2 Design Requirements
        1. 7.2.2.1 Clock Requirements
          1. 7.2.2.1.1 Oscillator
          2. 7.2.2.1.2 Crystal
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Signal Traces
        2. 7.4.1.2 Return Path
        3. 7.4.1.3 Metal Pour
        4. 7.4.1.4 PCB Layer Stacking
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Requirements

(1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
POWER-UP TIMING (Single  and Dual  supply mode)
T1 Supply ramp delay offset: For all supplies  (DVDD, VDDA, VDDIO) First Supply ramp to last supply ramp 200 ms
T2 Last Supply powerup to RESET Complete and SMI ready: Post power-up stabilization time prior to MDC preamble for register access 60 ms
T4 Supply ramp rate: For all supplies (DVDD, VDDA, VDDIO) (20% to 80%) 0.2 40 ms
Powerup to Strap latchin: Hardware configuration pins transition to output drivers 60 ms
Pedestal Voltage on DVDD, VDDA, VDDIO before Power Ramp 0.3 V
RESET TIMING
T1 RESET PULSE Width: Miminum Reset pulse width to be able to reset 10 us
T2 Reset to SMI ready: Post reset stabilization time prior to MDC preamble for register access 30 us
Reset to Strap latchin: Hardware configuration pins transition to output drivers 1050 ns
Reset to 10Base-T1L Auto Neg Signalling 9000 us
Reset to RMII Master clock 35 us
MII 10M Timings
T1 TX_CLK High / Low Time 190 200 210 ns
T2 TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK 25 ns
T3 TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK 0 ns
T1 RX_CLK High / Low Time 160 200 240 ns
T2 RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising 100 300 ns
RGMII OUTPUT TIMING (10M)
TskewT Data to Clock Output Skew (Non-Delay Mode) 5 pF Load -2 2 ns
TskewT (delay) Data to Clock Output Skew (Integrated Delay Mode) 5 pF Load 40 ns
Tcyc Clock Cycle Duration -360 400 440 ns
Duty Cycle 45 50 55 %
Rise / Fall Time ( 20% to 80%) 3 ns
RGMII INPUT TIMING (10M)
TskewR TX data to clock input skew  (Integrated Delay Mode) -4 4 ns
TsetupR TX data to clock input setup (Non-Delay Mode) 40 ns
TholdR TX clock to data input hold (Non-Delay Mode) 40 ns
RMII MASTER TIMING
T1 RMII Master Clock Period 20 ns
RMII Master Clock Duty Cycle 35 65 %
T2 TX_D[1:0], TX_ER, TX_EN Setup to RMII Master Clock 25 pF Load 4 ns
T3 TX_D[1:0], TX_ER, TX_EN Hold from RMII Master Clock 25 pF Load 2 ns
T4 RX_D[1:0], RX_ER, CRS_DV Delay from RMII Master Clock rising edge 25 pF Load 4 10 14 ns
RMII SLAVE TIMING
T1 Input Reference Clock Period 20 ns
Reference Clock Duty Cycle 35 65 %
T2 TX_D[1:0], TX_ER, TX_EN Setup to XI Clock rising 4 ns
T3 TX_D[1:0], TX_ER, TX_EN Hold from XI Clock rising 2 ns
T4 RX_D[1:0], RX_ER, CRS_DV Delay from XI Clock rising 4 14 ns
RMII Master Timing ( 5 MHz)
Frequency 5 MHz
Duty Cycle 40 60 %
T2 TX_D[3:0], TX_ER, TX_EN setup to Master Clock 10 ns
T3 TX_D[3:0], TX_ER, TX_EN hold from Master Clock 10 ns
T4 RX_D[3:0], RX_ER, RX_DV Delay from 5 MHz Clock 50 100 150 ns
SMI TIMING
T1 MDC to MDIO (Output) Delay Time 0 10 ns
T2 MDIO (Input) to MDC Setup Time 10 ns
T3 MDIO (Input) to MDC Hold Time 10 ns
T4 MDC Frequency 1 1.75 MHz
OUTPUT CLOCK TIMING (25MHz clockout)
Frequency (PPM) -100 100 -
Duty Cycle 40 60 %
Rise Time 5000 ps
Fall Time 5000 ps
Jitter (RMS - long term) 40 ps
Frequency 25 MHz
RefCLK to clock out delay 3000 ps
Output Clock 50 MHz timing
Frequency (PPM) -50 50 ppm
Duty Cycle 35 65 %
Rise time 5000 ps
Fall Time 5000 ps
Jitter (Long Term 10,000 Cyles) 650 ps
25MHz INPUT CLOCK tolerance
Frequency Tolerance -100 +100 ppm
Jitter Tolerance (RMS) 40 ps
Rise / Fall Time (10%-90%) 8 ns
Jitter Tolerance (Accumulated) 500 ps
Duty Cycle 40 60 %
50MHz Input Clock Tolerance
Frequency Tolerance -100 +100 ppm
Jitter Tolerance (RMS) 40 ps
Rise / Fall Time (10%-90%) 4 ns
Jitter Tolerance (Accumulated) 250 ps
Duty Cycle 40 60 %
TRANSMIT LATENCY TIMING
Copper RGMII to Cu (10M) : Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI 3000 ns
Copper MII to Cu (10M): Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI 750 ns
Tx_RMII Slave RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI (10M) 2800 ns
Tx_RMII Master RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI (10M) 2800 ns
RECEIVE LATENCY TIMING
Copper Cu to RGMII (10M): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_CTRL 5000 ns
Copper Cu to MII (10M): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_DV 5100 ns
Rx_RMII SSD symbol on MDI to Slave RMII Rising edge of XI clock with assertion of CRS_DV (10M) 5700 ns
Rx_RMII SSD symbol on MDI to Master RMII Rising edge of Master clock with assertion of CRS_DV (10M) 5800 ns
(1) Ensured by production test, characterization or design