SNLS603 Data sheet

BASE Registers lists the Base registers. All register offset addresses not listed in BASE Registers should be considered as reserved locations and the register contents should not be modified.

IEEE defined base register set as per 802.3 clause 22. These registers provide basic status, control, and identification functions.

Table 8-152 BASE Registers

Offset	Acronym	Section
0x0	Basic_Mode_Control_	Go
0x1	Basic_Mode_Status_	Go
0x2	PHY_Identification__1	Go
0x3	PHY_Identification__2	Go
0xD	Extended__Control_Register	Go
0xE	Address_or_Data_	Go
0x10	PHY_Control_	Go
0x11	PHY_Configuration_	Go
0x12	Interrupt_Status__1	Go
0x13	Interrupt_Status__2	Go
0x16	Loopback_Control_	Go
0x18	Interrupt_Status__3	Go
0x1E	TDR_Control_	Go
0x1F	PHY_Reset_	Go
0x180	Receiver_Status_	Go

Complex bit access types are encoded to fit into small table cells. Table 8-153 shows the codes that are used for access types in this section.

Table 8-153 Base Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
W0C	W0C	Write 0 to clear
W0S	W0S	Write 0 to set
WMC	W	Write with manual clear to default (refer to register description to know about the clearing event)
WMC,0	W	Write with manual clear to 0 (refer to register description to know about the clearing event)
WMC,1	W	Write with manual clear to 1 (refer to register description to know about the clearing event)
WSC	W	Write
WSC,0	W	Write with self clear to 0
Reset or Default Value
-n		Value after reset or the default value

6.2.1.1 Basic_Mode_Control_ Register (Offset = 0x0) [reset = 0x140]

Basic_Mode_Control_ is shown in Table 8-154.

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Table 8-154 Basic_Mode_Control_ Register Field Descriptions

Bit	Field	Type	Reset	Description
15	MII Reset	R/WMC	0x0	MII Reset 0x0 = No reset 0x1 = Digital in reset and all MII regs (0x0 - 0xF) reset to default
14	MII Loopback Enable	R/W	0x0	MII loopback enable 0x0 = No MII loopback 0x1 = MII loopback
13	Speed Selection LSB	R	0x0	Speed selection LSB 0x2 = 1000 Mb/s
12	RESERVED	R	0x0	Reserved
11	Power Down Mode Enable	R/W	0x0	Power down mode enable 0x0 = Normal mode 0x1 = Power down via register or pin
10	Isolate Mode Enable	R/W	0x0	Isolate mode enable 0x0 = Normal mode 0x1 = Isolate mode
9	RESERVED	R	0x0	Reserved
8	Duplex Mode	R	0x1	Duplex mode 0x0 = Half duplex 0x1 = Full duplex
7	RESERVED	R	0x0	Reserved
6	Speed Selection MSB	R	0x1	Speed selection MSB 0x2 = 1000 Mb/s
5	RESERVED	R	0x0	Reserved
4-0	RESERVED	R	0x0	Reserved

6.2.1.2 Basic_Mode_Status_ Register (Offset = 0x1) [reset = 0x141]

Basic_Mode_Status_ is shown in Table 8-155.

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Table 8-155 Basic_Mode_Status_ Register Field Descriptions

Bit	Field	Type	Reset	Description
15	100BASE-T4	R	0x0	100BASE-T4 0x0 = PHY not able to perform 100BASE-T4 0x1 = PHY able to perform 100BASE-T4
14	100BASE-TX Full-Duplex	R	0x0	100BASE-TX Full-Duplex 0x0 = PHY not able to perform full duplex 100BASE-X 0x1 = PHY able to perform full duplex 100BASE-X
13	100BASE-TX Half-Duplex	R	0x0	100BASE-TX Half-Duplex 0x0 = PHY not able to perform half duplex 100BASE-X 0x1 = PHY able to perform half duplex 100BASE-X
12	10BASE-T Full-Duplex	R	0x0	10BASE-T Full-Duplex 0x0 = PHY not able to operate at 10 Mb/s in full duplex mode 0x1 = PHY able to operate at 10 Mb/s in full duplex mode
11	10BASE-T Half-Duplex	R	0x0	10BASE-T Half-Duplex 0x0 = PHY not able to operate at 10 Mb/s in half duplex mode 0x1 = PHY able to operate at 10 Mb/s in half duplex mode
10	100BASE-T2 Full-Duplex	R	0x0	100BASE-T2 Full-Duplex 0x0 = PHY not able to perform full duplex 100BASE-T2 0x1 = PHY able to perform full duplex 100BASE-T2
9	100BASE-T2 Half-Duplex	R	0x0	100BASE-T2 Half-Duplex 0x0 = PHY not able to perform half duplex 100BASE-T2 0x1 = PHY able to perform half duplex 100BASE-T2
8	Extended Status Ready	R	0x1	Extended status in register 0xf 0x0 = No extended status information in Register 0xF 0x1 = Extended status information in Register 0xF
7	RESERVED	R	0x0	Reserved
6	SMI Preamble Supression	R	0x1	SMI preamble supression 0x0 = PHY will not accept management frames with preamble suppressed 0x1 = PHY will accept management frames with preamble suppressed.
5	RESERVED	R	0x0	Reserved
4	RESERVED	R/W0C	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	Link Status	R/W0S	0x0	Link status, latch low 0x0 = link had been down 0x1 = link is up
1	RESERVED	R/W0C	0x0	Reserved
0	Extended Capability	R	0x1	Extended capabilities status 0x0 = basic register set capabilities only 0x1 = extended register capabilities

6.2.1.3 PHY_Identification__1 Register (Offset = 0x2) [reset = 0x2000]

PHY_Identification__1 is shown in Table 8-156.

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Table 8-156 PHY_Identification__1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Organizationally Unique Identifier Bits [21:6]	R	0x2000

6.2.1.4 PHY_Identification__2 Register (Offset = 0x3) [reset = 0xA000]

PHY_Identification__2 is shown in Table 8-157.

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Table 8-157 PHY_Identification__2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	Organizationally Unique Identifier Bits [5:0]	R	0x28
9-4	Model Number	R	0x0	Vendor Model Number: The six bits of vendor model number are mapped from bits 9 to 4
3-0	Revision Number	R	0x0	Model Revision Number: Four bits of the vendor model revision number are mapped from bits 3 to 0. This field is incremented for all major device changes.

6.2.1.5 Extended__Control_Register Register (Offset = 0xD) [reset = 0x0]

Extended__Control_Register is shown in Table 8-158.

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Table 8-158 Extended__Control_Register Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	Extended Register Command	R/W	0x0	Extended Register Command: 0x0 = Address 0x1 = Data, no post increment 0x2 = Data, post increment on read and write 0x3 = Data, post increment on write only
13-5	RESERVED	R	0x0	Reserved
4-0	DEVAD	R/W	0x0	Device Address: Bits[4:0] are the device address, DEVAD, that directs any access of ADDAR Register 0x000E - Address/Data Register to the appropriate MMD. Specifically, the DP83TC811S-Q1 uses the vendor specific DEVAD [4:0] = "11111" for access to registers 0x04D1 and lower. For MMD1 access the DEVAD[4:0] = "00001". All accesses through registers REGCR and ADDAR should use the DEVAD for either MMD or MMD1. Transactions with other DEVAD are ignored.

Bit

Field

Type

Reset

Description

15-14

Extended Register Command

R/W

0x0

Extended Register Command:

0x0 = Address

0x1 = Data, no post increment

0x2 = Data, post increment on read and write

0x3 = Data, post increment on write only

13-5

RESERVED

R

0x0

Reserved

4-0

DEVAD

R/W

0x0

Device Address: Bits[4:0] are the device address, DEVAD, that directs any access of ADDAR Register 0x000E - Address/Data Register to the appropriate MMD. Specifically, the DP83TC811S-Q1 uses the vendor specific DEVAD [4:0] = "11111" for access to registers 0x04D1 and lower. For MMD1 access the DEVAD[4:0] = "00001". All accesses through registers REGCR and ADDAR should use the DEVAD for either MMD or MMD1. Transactions with other DEVAD are ignored.

6.2.1.6 Address_or_Data_ Register (Offset = 0xE) [reset = 0x0]

Address_or_Data_ is shown in Table 8-159.

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Table 8-159 Address_or_Data_ Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Address/Data	R/W	0x0	If REGCR register 15:14 = '00', holds the MMD DEVAD's address register, otherwise holds the MMD DEVAD's data.

6.2.1.7 PHY_Control_ Register (Offset = 0x10) [reset = 0x4]

PHY_Control_ is shown in Table 8-160.

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Table 8-160 PHY_Control_ Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0x0	Reserved
10	Channel OK	R/W0S	0x0	Channel ok, latched low 0x0 = Channel ok had been reset 0x1 = Channel ok is set
9	Descrambler Lock	R/W0S	0x0	Descrambler lock, latched low 0x0 = Descrmabler had been locked 0x1 = Descrambler is locked
8	RESERVED	R	0x0	Reserved
7	Interrupt Pin Status		0x0	Interrupts pin status, cleared on reading register 0x12 0x0 = Interrupts pin not set 0x1 = Interrupt pin had been set
6-4	RESERVED	R	0x0	Reserved
3	MII Loopback Status	R	0x0	MII loopback status 0x0 = No MII loopback 0x1 = MII loopback
2	Duplex Mode Status	R	0x1	Duplex mode status 0x0 = Half duplex 0x1 = Full duplex
1	RESERVED	R	0x0	Reserved
0	Link Status	R	0x0	Link status 0x0 = link had been down 0x1 = link is up

6.2.1.8 PHY_Configuration_ Register (Offset = 0x11) [reset = 0x8]

PHY_Configuration_ is shown in Table 8-161.

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Table 8-161 PHY_Configuration_ Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Disable MAC Clock	R/W	0x0	Disable MAC clock 0x0 = keep clk_125 to MAC 0x1 = stop clk_125 to MAC on IEEE power save mode
14	Enable Force Power Mode	R/W	0x0	Enable power save mode config from reg
13-11	RESERVED	R/W	0x0	Reserved Must be written as 0x0
10-4	RESERVED	R	0x0	Reserved
3	Interrupt Pin Polarity	R/W	0x1	Interrupt pin polarity 0x0 = Active high 0x1 = Active low
2	Force Interrupt Pin	R/W	0x0	Force interrupt pin 0x0 = Do not force interrupt pin 0x1 = Force interrupt pin
1	Interrupt Enable	R/W	0x0	Enable interrupts 0x0 = Disable interrupts 0x1 = Enable interrupts
0	RESERVED	R/W	0x0	Reserved Must be written as 0x0

6.2.1.9 Interrupt_Status__1 Register (Offset = 0x12) [reset = 0x0]

Interrupt_Status__1 is shown in Table 8-162.

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Table 8-162 Interrupt_Status__1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Link Quality Low Interrupt	R	0x0	Link quality low interrupt status
14	Energy Detect Interrupt	R	0x0	Energy det change interrupt status
13	Link Status Changed Interrupt	R	0x0	Link status change interrupt status
12	RESERVED	R	0x0	Reserved
11	ESD Event Interrupt	R	0x0	ESD fault detected interrupt status
10	1000BASE-T1 Link Training Done Interrupt	R	0x0	Training done interrupt status
9-8	RESERVED	R	0x0	Reserved
7	Link Quality Interrupt Enable	R/W	0x0	Link quality bad interrupt enable
6	Energy Detect Interrupt Enable	R/W	0x0	Energy det change interrupt enable
5	Link Status Changed Interrupt Enable	R/W	0x0	Link status change interrupt enable
4	RESERVED	R	0x0	Reserved
3	ESD Event Interrupt Enable	R/W	0x0	ESD fault detected interrupt enable
2	1000BASE-T1 Link Training Done Enable	R/W	0x0	Training done interrupt enable
1-0	RESERVED	R	0x0	Reserved

6.2.1.10 Interrupt_Status__2 Register (Offset = 0x13) [reset = 0x0]

Interrupt_Status__2 is shown in Table 8-163.

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Table 8-163 Interrupt_Status__2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Undervoltage Interrupt	R	0x0	Under volt interrupt status
14	Overvoltage Interrupt	R	0x0	Over volt interrupt status
13-12	RESERVED	R	0x0	Reserved
11	Overtemperature Interrupt	R	0x0	Over temp interrupt status
10	Sleep Mode Change Interrupt	R	0x0	Sleep mode change interrupt status
9	RESERVED	R	0x0	Reserved
8	not_one_hot_int	R	0x0	Not one hot interrupt status
7	Undervoltage Interrupt Enable	R/W	0x0	Under volt interrupt enable
6	Overvoltage Interrupt Enable	R/W	0x0	Over volt interrupt enable
5-4	RESERVED	R	0x0	Reserved
3	Overtemperature Interrupt Enable	R/W	0x0	Over temp interrupt enable
2	Sleep Mode Change Interrupt Enable	R/W	0x0	Sleep mode change interrupt enable
1-0	RESERVED	R	0x0	Reserved

6.2.1.11 Loopback_Control_ Register (Offset = 0x16) [reset = 0x0]

Loopback_Control_ is shown in Table 8-164.

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Table 8-164 Loopback_Control_ Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0x0	Reserved
10	PRBS Checker Sync Loss	R/W0C	0x0	PRBS Checker Sync Loss Indication: 0x0 = PRBS checker has not lost sync 0x1 = PRBS checker has lost sync
9	RESERVED	R	0x0	Reserved
8	Core Power Mode	R	0x0	1b = Core is is normal power mode 0b = Core is in power down or sleep mode 0x0 = Core is in power down or sleep mode 0x1 = Core is is normal power mode
7	PCS Digital Loopback Enable	R/W	0x0	PCS digital loopback 0x0 = PCS digital loopback disabled 0x1 = PCS digital loopback enabled
6	Transmit Data In Loopback Enable	R/W	0x0	Transmit MII loopback data to MDI. This bit should only be used when in MII loopback mode. 0x0 = Suppress data to MDI 0x1 = Transmit data to MDI
5-0	Loopback Select	R/W	0x0	Loopback mode selection: 0x1 = PCS loop 0x2 = RS loop 0x4 = Digital loop 0x8 = Analog loop 0x10 = Reverse loop 0x20 = Ext Reverse loop

6.2.1.12 Interrupt_Status__3 Register (Offset = 0x18) [reset = 0x8]

Interrupt_Status__3 is shown in Table 8-165.

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Table 8-165 Interrupt_Status__3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Ack Received Interrupt	R	0x0	Ack received interrupt status (OAM)
14	TX Valid CLR Interrupt	R	0x0	mr_tx_valid clear interrupt status (OAM)
13-12	RESERVED	R	0x0	Reserved
11	POR Done Interrupt	R	0x0	POR done interrupt status
10	No Frame Interrupt	R	0x0	No frame detect interrupt status
9	Wake Request Interrupt	R	0x0	Wake request interrupt status
8	LPS Interrupt	R	0x0	LPS interrupt status
7	Ack Received Interrupt Enable	R/W	0x0	Ack received interrupt enable (OAM)
6	TX Valid CLR Interrupt Enable	R/W	0x0	mr_tx_valid clear interrupt enable (OAM)
5-4	RESERVED	R	0x0	Reserved
3	POR Done Interrupt Enable	R/W	0x1	POR done interrupt enable
2	No Frame Interrupt Enable	R/W	0x0	No frame detect interrupt enable
1	Wake Request Interrupt Enable	R/W	0x0	Wake request interrupt enable
0	LPS Interrupt Enable	R/W	0x0	LPS interrupt enable

6.2.1.13 TDR_Control_ Register (Offset = 0x1E) [reset = 0x0]

TDR_Control_ is shown in Table 8-166.

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Table 8-166 TDR_Control_ Register Field Descriptions

Bit	Field	Type	Reset	Description
15	TDR Start	R/WMC	0x0	Start TDR manually 0x0 = No TDR 0x1 = TDR start
14	TDR Auto Run Enable	R/W	0x0	Enable TDR auto run on link down 0x0 = TDR start manually 0x1 = TDR start automatically on link down
13-2	RESERVED	R	0x0	Reserved
1	TDR Done	R	0x0	TDR Done: 0x0 = Cable diagnostic has not completed 0x1 = Indication that cable measurement process is complete
0	TDR Test Fail	R	0x0	TDR Test Fail: 0x0 = TDR has not suffered a failure 0x1 = TDR cable measurement process has failed

6.2.1.14 PHY_Reset_ Register (Offset = 0x1F) [reset = 0x0]

PHY_Reset_ is shown in Table 8-167.

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Table 8-167 PHY_Reset_ Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Hardware Reset	R/WMC	0x0	Hardware Reset: 0x0 = Normal operation 0x1 = Reset PHY. This bit is self cleared and has the same effect as the RESET_N pin.
14	Software Restart	R/WMC	0x0	Software Restart: 0x0 = Normal operation 0x1 = Restart PHY. This bit is self cleared and resets all PHY circuitry except current control register values.
13-0	RESERVED	R/W	0x0	Reserved Must be written as 0x0

Bit

Field

Type

Reset

Description

15

Hardware Reset

R/WMC

0x0

Hardware Reset:

0x0 = Normal operation

0x1 = Reset PHY. This bit is self cleared and has the same effect as the RESET_N pin.

14

Software Restart

R/WMC

0x0

Software Restart:

0x0 = Normal operation

0x1 = Restart PHY. This bit is self cleared and resets all PHY circuitry except current control register values.

13-0

RESERVED

R/W

0x0

Reserved
Must be written as 0x0

6.2.1.15 Receiver_Status_ Register (Offset = 0x180) [reset = 0x0]

Receiver_Status_ is shown in Table 8-168.

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Table 8-168 Receiver_Status_ Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0x0	Reserved
12	Link Status	R	0x0	Unlatched Link Status: 0x0 = No link 0x1 = Valid link established
11-3	RESERVED	R	0x0	Reserved
2	Descrambler Lock	R	0x0	Descrambler lock status: 0x0 = Descrambler not locked 0x1 = Descrambler locked on incoming symbols
1	Local Receiver Status	R	0x0	Local receiver status: 0x0 = Local PHY received invalid link 0x1 = Local PHY received valid link
0	Remote Receiver Status	R	0x0	Remote receiver status: 0x0 = Remote PHY received invalid link 0x1 = Remote PHY received valid link

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8.6.2.1 Base Registers

6.2.1.1 Basic_Mode_Control_ Register (Offset = 0x0) [reset = 0x140]

6.2.1.2 Basic_Mode_Status_ Register (Offset = 0x1) [reset = 0x141]

6.2.1.3 PHY_Identification__1 Register (Offset = 0x2) [reset = 0x2000]

6.2.1.4 PHY_Identification__2 Register (Offset = 0x3) [reset = 0xA000]

6.2.1.5 Extended__Control_Register Register (Offset = 0xD) [reset = 0x0]

6.2.1.6 Address_or_Data_ Register (Offset = 0xE) [reset = 0x0]

6.2.1.7 PHY_Control_ Register (Offset = 0x10) [reset = 0x4]

6.2.1.8 PHY_Configuration_ Register (Offset = 0x11) [reset = 0x8]

6.2.1.9 Interrupt_Status__1 Register (Offset = 0x12) [reset = 0x0]

6.2.1.10 Interrupt_Status__2 Register (Offset = 0x13) [reset = 0x0]

6.2.1.11 Loopback_Control_ Register (Offset = 0x16) [reset = 0x0]

6.2.1.12 Interrupt_Status__3 Register (Offset = 0x18) [reset = 0x8]

6.2.1.13 TDR_Control_ Register (Offset = 0x1E) [reset = 0x0]

6.2.1.14 PHY_Reset_ Register (Offset = 0x1F) [reset = 0x0]

6.2.1.15 Receiver_Status_ Register (Offset = 0x180) [reset = 0x0]