SNLS603C December 2020 – November 2022 DP83TG720R-Q1
PRODUCTION DATA
Test mode 7 enabled bit error rate measurement on a link segment. This mode uses zero data pattern on the MDI to check BER by comparing an expected zero data pattern to any non-zero bit received. Error checking is performed after FEC and 80B/81B decoding.
MMD | Register | Value | Test Mode |
---|---|---|---|
MMD1 | 0x0904 | 0x2000 | Test Mode 1 : Tx_Tclk 125MHz is routed to clkout pin. |
MMD1 | 0x0904 | 0x4000 | Test Mode 2 |
MMD1 | 0x0904 | 0x8000 | Test Mode 4 : Tx_Tclk 125MHz is routed to clkout pin. |
MMD1F | 0x0453 | 0x0019 | |
MMD1 | 0x0904 | 0xA000 | Test Mode 5 |
MMD1 | 0x0904 | 0xC000 | Test Mode 6 |
MMD1 | 0x0904 | 0xE000 | Test Mode 7 |