SNLS603C December   2020  – November 2022 DP83TG720R-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Pin States
    3. 6.2 Pin Power Domain
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 LED Drive Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Diagnostic Tool Kit
        1. 8.3.1.1 Signal Quality Indicator
        2. 8.3.1.2 Time Domain Reflectometry
        3. 8.3.1.3 Built-In Self-Test For Datapath
          1. 8.3.1.3.1 Loopback Modes
          2. 8.3.1.3.2 Data Generator
          3. 8.3.1.3.3 Programming Datapath BIST
        4. 8.3.1.4 Temperature and Voltage Sensing
        5. 8.3.1.5 Electrostatic Discharge Sensing
      2. 8.3.2 Compliance Test Modes
        1. 8.3.2.1 Test Mode 1
        2. 8.3.2.2 Test Mode 2
        3. 8.3.2.3 Test Mode 4
        4. 8.3.2.4 Test Mode 5
        5. 8.3.2.5 Test Mode 6
        6. 8.3.2.6 Test Mode 7
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Down
      2. 8.4.2  Reset
      3. 8.4.3  Standby
      4. 8.4.4  Normal
      5. 8.4.5  Sleep
      6. 8.4.6  State Transitions
        1. 8.4.6.1 State Transition #1 - Standby to Normal
        2. 8.4.6.2 State Transition #2 - Normal to Standby
        3. 8.4.6.3 State Transition #3 - Normal to Sleep
        4. 8.4.6.4 State Transition #4 - Sleep to Normal
      7. 8.4.7  Media Dependent Interface
        1. 8.4.7.1 MDI Master and MDI Slave Configuration
        2. 8.4.7.2 Auto-Polarity Detection and Correction
      8. 8.4.8  MAC Interfaces
        1. 8.4.8.1 Reduced Gigabit Media Independent Interface
      9. 8.4.9  Serial Management Interface
      10. 8.4.10 Direct Register Access
      11. 8.4.11 Extended Register Space Access
      12. 8.4.12 Write Address Operation
        1. 8.4.12.1 Example - Write Address Operation
      13. 8.4.13 Read Address Operation
        1. 8.4.13.1 Example - Read Address Operation
      14. 8.4.14 Write Operation (No Post Increment)
        1. 8.4.14.1 Example - Write Operation (No Post Increment)
      15. 8.4.15 Read Operation (No Post Increment)
        1. 8.4.15.1 Example - Read Operation (No Post Increment)
      16. 8.4.16 Write Operation (Post Increment)
        1. 8.4.16.1 Example - Write Operation (Post Increment)
      17. 8.4.17 Read Operation (Post Increment)
        1. 8.4.17.1 Example - Read Operation (Post Increment)
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Register Access Summary
      2. 8.6.2 DP83TG720 Registers
        1. 8.6.2.1 Base Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Compatibility with TI's 100BT1 PHY
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
      2. 12.1.2 Return Path
      3. 12.1.3 Physical Medium Attachment
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
      1. 14.1.1 Packaging Information
      2. 14.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.6.4 State Transition #4 - Sleep to Normal

Sleep state can be exited either locally (pin/register-write) or by remote link-partner.

Local Sleep Exit

Local sleep exit for Master mode PHY by :

  • Making "wake" pin high (3.3V).

Local sleep exit for Slave mode PHY by :

  • Making "wake" pin high (3.3V).

Remote Sleep Exit

Device can be made to exit the sleep mode by link-partner by either of the following :

  1. Remote sleep exit using Send-S symbols from link-partner.
  2. Remote sleep exit using Send-T symbols from link-partner

    Details of these procedures are in the following table :

    Table 8-8 Remote Sleep Exit Procedures
    Method Device Mode Procedure Required Link-partner Cabability
    Using Send-S Master

    Step 1 : Start IEEE defined Send-S pattern from link-partner for atleast 1.25ms.

    Step 2 : Put link-partner in the normal mode to start the link-up.

    Note : Link-partner with low VOD may limit the remote wake-up upto a maximum of 5m cable.

    		 Link-partner needs to have a mode to send Send-S pattern on demand in Slave mode also.

    One possible way is :

    Step 1 : Put link-partner in master mode for atleast 1.25ms.

    Step 2 : Put link-partner in normal mode to start the link-up
    Slave

    Step 1 : Start IEEE defined Send-S pattern from link-partner for atleast 1.25ms.

    Step 2 : Put link-partner in the normal mode to start the link-up.

    Note : Link-partner with low VOD may limit the remote wake-up upto a maximum of 5m cable.

    Note : To keep the slave mode DP83TG720 in sleep mode, link-partner can be put in managed mode (where device is not allowed to start link-up sequence).

    		 Any IEEE compliant link-partner will work, as master mode link-partner is supposed to send Send-S signals to start the link-up
    Using Send-T Master

    Step 1 : Enable Send-T pattern on link-partner for atleast 1.25ms.

    Step 2 : Put link-partner in the normal mode to start the link-up.

    		Link-partner needs to have a mode to send Send-T pattern on demand.

    Swing during Send-T mode at pins of link-partner should be greater than 0.92V for remote wake-up over 15m cable. Link-partner with lower VOD may limit the remote wake-up to 5m cable.

    DP83T720 as link-partner can do the required with following steps :

    Step 1 : Enable Send-T pattern on DP83TG720 link-partner : write reg[0x0405]=0x7400; reg[0x0509]=0x4007 and reg[0x0576]=0x0500

    Step 2 : After 100ms disable send-T pattern on DP83TG720 link-partner : write reg[0x0405]=x5800; reg[0x0509]=0x4005 and reg[0x0576]=0x0000
    Slave

    Step 1 : Enable Send-T pattern on link-partner for atleast 1.25ms.

    Step 2 : Put link-partner in the normal mode to start the link-up.

    		Link-partner needs to have a mode to send Send-T pattern on demand.

    Swing during Send-T mode at pins of link-partner should be greater than 0.92V for remote wake-up over 15m cable. Link-partner with lower VOD may limit the remote wake-up to 5m cable.

    DP83T720 as link-partner can do the required with following steps :

    Step 1 : Enable Send-T pattern on DP83TG720 link-partner : write reg[0x0405]=0x7400; reg[0x0509]=0x4007 and reg[0x0576]=0x0500

    Step 2 : After 100ms disable send-T pattern on DP83TG720 link-partner : write reg[0x0405]=x5800; reg[0x0509]=0x4005 and reg[0x0576]=0x0000