SPRS960 Data sheet

SPRS960G June 2016 – November 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

CBD|538

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprs960g_oa

4.3.5 EMIF

NOTE

For more information, see the Memory Subsystem / EMIF Controller section of the device TRM.

NOTE

The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Table 4-6, EMIF Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 type of SDRAM memories.

Table 4-6 EMIF Signal Descriptions

SIGNAL NAME	DESCRIPTION	TYPE	BALL
ddr1_csn0	EMIF1 Chip Select 0	O	AC19
ddr1_cke	EMIF1 Clock Enable	O	AB18
ddr1_ck	EMIF1 Clock	O	AD21
ddr1_nck	EMIF1 Negative Clock	O	AE21
ddr1_odt0	EMIF1 On-Die Termination for Chip Select 0	O	AD18
ddr1_casn	EMIF1 Column Address Strobe	O	AD16
ddr1_rasn	EMIF1 Row Address Strobe	O	AD17
ddr1_wen	EMIF1 Write Enable	O	AE18
ddr1_rst	EMIF1 Reset output (DDR3-SDRAM only)	O	AE17
ddr1_ba0	EMIF1 Bank Address	O	AE16
ddr1_ba1	EMIF1 Bank Address	O	AA16
ddr1_ba2	EMIF1 Bank Address	O	AB16
ddr1_a0	EMIF1 Address Bus	O	AC18
ddr1_a1	EMIF1 Address Bus	O	AE19
ddr1_a2	EMIF1 Address Bus	O	AD19
ddr1_a3	EMIF1 Address Bus	O	AB19
ddr1_a4	EMIF1 Address Bus	O	AD20
ddr1_a5	EMIF1 Address Bus	O	AE20
ddr1_a6	EMIF1 Address Bus	O	AA18
ddr1_a7	EMIF1 Address Bus	O	AA20
ddr1_a8	EMIF1 Address Bus	O	Y21
ddr1_a9	EMIF1 Address Bus	O	AC20
ddr1_a10	EMIF1 Address Bus	O	AA21
ddr1_a11	EMIF1 Address Bus	O	AC21
ddr1_a12	EMIF1 Address Bus	O	AC22
ddr1_a13	EMIF1 Address Bus	O	AC15
ddr1_a14	EMIF1 Address Bus	O	AB15
ddr1_a15	EMIF1 Address Bus	O	AC16
ddr1_d0	EMIF1 Data Bus	IO	AA23
ddr1_d1	EMIF1 Data Bus	IO	AC24
ddr1_d2	EMIF1 Data Bus	IO	AB24
ddr1_d3	EMIF1 Data Bus	IO	AD24
ddr1_d4	EMIF1 Data Bus	IO	AB23
ddr1_d5	EMIF1 Data Bus	IO	AC23
ddr1_d6	EMIF1 Data Bus	IO	AD23
ddr1_d7	EMIF1 Data Bus	IO	AE24
ddr1_d8	EMIF1 Data Bus	IO	AA24
ddr1_d9	EMIF1 Data Bus	IO	W25
ddr1_d10	EMIF1 Data Bus	IO	Y23
ddr1_d11	EMIF1 Data Bus	IO	AD25
ddr1_d12	EMIF1 Data Bus	IO	AC25
ddr1_d13	EMIF1 Data Bus	IO	AB25
ddr1_d14	EMIF1 Data Bus	IO	AA25
ddr1_d15	EMIF1 Data Bus	IO	W24
ddr1_d16	EMIF1 Data Bus	IO	W23
ddr1_d17	EMIF1 Data Bus	IO	U25
ddr1_d18	EMIF1 Data Bus	IO	U24
ddr1_d19	EMIF1 Data Bus	IO	W21
ddr1_d20	EMIF1 Data Bus	IO	T22
ddr1_d21	EMIF1 Data Bus	IO	U22
ddr1_d22	EMIF1 Data Bus	IO	U23
ddr1_d23	EMIF1 Data Bus	IO	T21
ddr1_d24	EMIF1 Data Bus	IO	T23
ddr1_d25	EMIF1 Data Bus	IO	T25
ddr1_d26	EMIF1 Data Bus	IO	T24
ddr1_d27	EMIF1 Data Bus	IO	P21
ddr1_d28	EMIF1 Data Bus	IO	N21
ddr1_d29	EMIF1 Data Bus	IO	P22
ddr1_d30	EMIF1 Data Bus	IO	P23
ddr1_d31	EMIF1 Data Bus	IO	P24
ddr1_dqm0	EMIF1 Data Mask	O	AE23
ddr1_dqm1	EMIF1 Data Mask	O	W22
ddr1_dqm2	EMIF1 Data Mask	O	U21
ddr1_dqm3	EMIF1 Data Mask	O	P25
ddr1_dqs0	Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AD22
ddr1_dqsn0	Data strobe 0 invert	IO	AE22
ddr1_dqs1	Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	Y24
ddr1_dqsn1	Data strobe 1 invert	IO	Y25
ddr1_dqs2	Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	V24
ddr1_dqsn2	Data strobe 2 invert	IO	V25
ddr1_dqs3	Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	R24
ddr1_dqsn3	Data strobe 3 invert	IO	R25
ddr1_vref0	Reference Power Supply EMIF1	A	Y20