SPRS960G June   2016  – November 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IVA
    6. 6.6  IPU
    7. 6.7  GPU
    8. 6.8  BB2D
    9. 6.9  PRU-ICSS
    10. 6.10 Memory Subsystem
      1. 6.10.1 EMIF
      2. 6.10.2 GPMC
      3. 6.10.3 ELM
      4. 6.10.4 OCMC
    11. 6.11 Interprocessor Communication
      1. 6.11.1 MailBox
      2. 6.11.2 Spinlock
    12. 6.12 Interrupt Controller
    13. 6.13 EDMA
    14. 6.14 Peripherals
      1. 6.14.1  VIP
      2. 6.14.2  DSS
      3. 6.14.3  Timers
        1. 6.14.3.1 General-Purpose Timers
        2. 6.14.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.14.3.3 Watchdog Timer
      4. 6.14.4  I2C
      5. 6.14.5  UART
        1. 6.14.5.1 UART Features
        2. 6.14.5.2 IrDA Features
        3. 6.14.5.3 CIR Features
      6. 6.14.6  McSPI
      7. 6.14.7  QSPI
      8. 6.14.8  McASP
      9. 6.14.9  USB
      10. 6.14.10 PCIe
      11. 6.14.11 DCAN
      12. 6.14.12 GMAC_SW
      13. 6.14.13 eMMC/SD/SDIO
      14. 6.14.14 GPIO
      15. 6.14.15 ePWM
      16. 6.14.16 eCAP
      17. 6.14.17 eQEP
    15. 6.15 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CBD|538
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.4 Pin Multiplexing

Table 4-32 describes the device pin multiplexing (no characteristics are provided in this table).

NOTE

Table 4-32, Pin Multiplexing doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.3, Signal Descriptions.

NOTE

For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration section of the Device TRM.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

NOTE

When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.

NOTE

In some cases Table 4-32 may present more than one signal per muxmode for the same ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_* register.

All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

Table 4-32 Pin Multiplexing (1)

ADDRESS REGISTER NAME BALL NUMBER MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15
P25 ddr1_dqm3
Y23 ddr1_d10
P21 ddr1_d27
T3 mlbp_sig_p
U25 ddr1_d17
AA20 ddr1_a7
V25 ddr1_dqsn2
AB16 ddr1_ba2
T25 ddr1_d25
N21 ddr1_d28
AB25 ddr1_d13
AE9 hdmi1_clockx
W23 ddr1_d16
AC24 ddr1_d1
AD16 ddr1_casn
AA23 ddr1_d0
AD18 ddr1_odt0
AE19 ddr1_a1
AC20 ddr1_a9
U21 ddr1_dqm2
AA24 ddr1_d8
U4 mlbp_sig_n
AC11 xi_osc1
AD1 csi2_0_dx1
AE3 usb_txn0 pcie_txn1
AC6 usb1_dp
AD6 usb_rxp0 pcie_rxp1
AA16 ddr1_ba1
Y12 xi_osc0
AB15 ddr1_a14
AC18 ddr1_a0
AE11 hdmi1_data0x
R25 ddr1_dqsn3
Y24 ddr1_dqs1
Y21 ddr1_a8
W21 ddr1_d19
AD20 ddr1_a4
AA25 ddr1_d14
AD13 hdmi1_data1y
AB9 ljcb_clkn
AC25 ddr1_d12
U22 ddr1_d21
AB23 ddr1_d4
AB24 ddr1_d2
AE16 ddr1_ba0
T22 ddr1_d20
T21 ddr1_d23
AB19 ddr1_a3
AE24 ddr1_d7
AC15 ddr1_a13
AC21 ddr1_a11
AD17 ddr1_rasn
AB12 xo_osc0
AD23 ddr1_d6
AD9 pcie_txp0
V24 ddr1_dqs2
U1 mlbp_clk_n
U23 ddr1_d22
T1 mlbp_dat_n
AC22 ddr1_a12
AD24 ddr1_d3
AC8 ljcb_clkp
AE21 ddr1_nck
Y20 ddr1_vref0
AD7 pcie_rxp0
T2 mlbp_dat_p
AE23 ddr1_dqm0
AD21 ddr1_ck
Y25 ddr1_dqsn1
AA11 xo_osc1
AE17 ddr1_rst
W22 ddr1_dqm1
AE12 hdmi1_data1x
AE14 hdmi1_data2x
AB2 csi2_0_dy0
AB18 ddr1_cke
AB6 usb2_dp
AC1 csi2_0_dx0
AE8 pcie_txn0
AC19 ddr1_csn0
AA21 ddr1_a10
AE6 pcie_rxn0
AB7 usb1_dm
F19 porz
W25 ddr1_d9
P24 ddr1_d31
AD22 ddr1_dqs0
P22 ddr1_d29
U24 ddr1_d18
AD2 csi2_0_dy2
AE18 ddr1_wen
AE20 ddr1_a5
W24 ddr1_d15
T24 ddr1_d26
R24 ddr1_dqs3
AD15 hdmi1_data2y
AE22 ddr1_dqsn0
AA18 ddr1_a6
U2 mlbp_clk_p
AC2 csi2_0_dy1
AD12 hdmi1_data0y
T23 ddr1_d24
AD10 hdmi1_clocky
AE5 usb_rxn0 pcie_rxn1
AE2 csi2_0_dx2
P23 ddr1_d30
AC5 usb2_dm
AC23 ddr1_d5
AD19 ddr1_a2
AC16 ddr1_a15
AD25 ddr1_d11
AD4 usb_txp0 pcie_txp1
0x1400 CTRL_CORE_PAD_GPMC_AD0 F1 gpmc_ad0 vin1a_d0 vout3_d0 gpio1_6 sysboot0
0x1404 CTRL_CORE_PAD_GPMC_AD1 E2 gpmc_ad1 vin1a_d1 vout3_d1 gpio1_7 sysboot1
0x1408 CTRL_CORE_PAD_GPMC_AD2 E1 gpmc_ad2 vin1a_d2 vout3_d2 gpio1_8 sysboot2
0x140C CTRL_CORE_PAD_GPMC_AD3 C1 gpmc_ad3 vin1a_d3 vout3_d3 gpio1_9 sysboot3
0x1410 CTRL_CORE_PAD_GPMC_AD4 D1 gpmc_ad4 vin1a_d4 vout3_d4 gpio1_10 sysboot4
0x1414 CTRL_CORE_PAD_GPMC_AD5 D2 gpmc_ad5 vin1a_d5 vout3_d5 gpio1_11 sysboot5
0x1418 CTRL_CORE_PAD_GPMC_AD6 B1 gpmc_ad6 vin1a_d6 vout3_d6 gpio1_12 sysboot6
0x141C CTRL_CORE_PAD_GPMC_AD7 B2 gpmc_ad7 vin1a_d7 vout3_d7 gpio1_13 sysboot7
0x1420 CTRL_CORE_PAD_GPMC_AD8 C2 gpmc_ad8 vin1a_d8 vout3_d8 gpio7_18 sysboot8
0x1424 CTRL_CORE_PAD_GPMC_AD9 D3 gpmc_ad9 vin1a_d9 vout3_d9 gpio7_19 sysboot9
0x1428 CTRL_CORE_PAD_GPMC_AD10 A2 gpmc_ad10 vin1a_d10 vout3_d10 gpio7_28 sysboot10
0x142C CTRL_CORE_PAD_GPMC_AD11 B3 gpmc_ad11 vin1a_d11 vout3_d11 gpio7_29 sysboot11
0x1430 CTRL_CORE_PAD_GPMC_AD12 C3 gpmc_ad12 vin1a_d12 vout3_d12 gpio1_18 sysboot12
0x1434 CTRL_CORE_PAD_GPMC_AD13 C4 gpmc_ad13 vin1a_d13 vout3_d13 gpio1_19 sysboot13
0x1438 CTRL_CORE_PAD_GPMC_AD14 A3 gpmc_ad14 vin1a_d14 vout3_d14 gpio1_20 sysboot14
0x143C CTRL_CORE_PAD_GPMC_AD15 B4 gpmc_ad15 vin1a_d15 vout3_d15 gpio1_21 sysboot15
0x1440 CTRL_CORE_PAD_GPMC_A0 M1 gpmc_a0 vin1a_d16 vout3_d16 vin1b_d0 i2c4_scl uart5_rxd gpio7_3 gpmc_a26 gpmc_a16 Driver off
0x1444 CTRL_CORE_PAD_GPMC_A1 M2 gpmc_a1 vin1a_d17 vout3_d17 vin1b_d1 i2c4_sda uart5_txd gpio7_4 Driver off
0x1448 CTRL_CORE_PAD_GPMC_A2 L2 gpmc_a2 vin1a_d18 vout3_d18 vin1b_d2 uart7_rxd uart5_ctsn gpio7_5 Driver off
0x144C CTRL_CORE_PAD_GPMC_A3 L1 gpmc_a3 qspi1_cs2 vin1a_d19 vout3_d19 vin1b_d3 uart7_txd uart5_rtsn gpio7_6 Driver off
0x1450 CTRL_CORE_PAD_GPMC_A4 K3 gpmc_a4 qspi1_cs3 vin1a_d20 vout3_d20 vin1b_d4 i2c5_scl uart6_rxd gpio1_26 Driver off
0x1454 CTRL_CORE_PAD_GPMC_A5 K2 gpmc_a5 vin1a_d21 vout3_d21 vin1b_d5 i2c5_sda uart6_txd gpio1_27 Driver off
0x1458 CTRL_CORE_PAD_GPMC_A6 J1 gpmc_a6 vin1a_d22 vout3_d22 vin1b_d6 uart8_rxd uart6_ctsn gpio1_28 Driver off
0x145C CTRL_CORE_PAD_GPMC_A7 K1 gpmc_a7 vin1a_d23 vout3_d23 vin1b_d7 uart8_txd uart6_rtsn gpio1_29 Driver off
0x1460 CTRL_CORE_PAD_GPMC_A8 K4 gpmc_a8 vin1a_hsync0 vout3_hsync vin1b_hsync1 timer12 spi4_sclk gpio1_30 Driver off
0x1464 CTRL_CORE_PAD_GPMC_A9 H1 gpmc_a9 vin1a_vsync0 vout3_vsync vin1b_vsync1 timer11 spi4_d1 gpio1_31 Driver off
0x1468 CTRL_CORE_PAD_GPMC_A10 J2 gpmc_a10 vin1a_de0 vout3_de vin1b_clk1 timer10 spi4_d0 gpio2_0 Driver off
0x146C CTRL_CORE_PAD_GPMC_A11 L3 gpmc_a11 vin1a_fld0 vout3_fld vin1b_de1 timer9 spi4_cs0 gpio2_1 Driver off
0x1470 CTRL_CORE_PAD_GPMC_A12 G1 gpmc_a12 gpmc_a0 vin1b_fld1 timer8 spi4_cs1 dma_evt1 gpio2_2 Driver off
0x1474 CTRL_CORE_PAD_GPMC_A13 H3 gpmc_a13 qspi1_rtclk timer7 spi4_cs2 dma_evt2 gpio2_3 Driver off
0x1478 CTRL_CORE_PAD_GPMC_A14 H4 gpmc_a14 qspi1_d3 timer6 spi4_cs3 gpio2_4 Driver off
0x147C CTRL_CORE_PAD_GPMC_A15 K6 gpmc_a15 qspi1_d2 timer5 gpio2_5 Driver off
0x1480 CTRL_CORE_PAD_GPMC_A16 K5 gpmc_a16 qspi1_d0 gpio2_6 Driver off
0x1484 CTRL_CORE_PAD_GPMC_A17 G2 gpmc_a17 qspi1_d1 gpio2_7 Driver off
0x1488 CTRL_CORE_PAD_GPMC_A18 F2 gpmc_a18 qspi1_sclk gpio2_8 Driver off
0x148C CTRL_CORE_PAD_GPMC_A19 A4 gpmc_a19 mmc2_dat4 gpmc_a13 vin2b_d0 gpio2_9 Driver off
0x1490 CTRL_CORE_PAD_GPMC_A20 E7 gpmc_a20 mmc2_dat5 gpmc_a14 vin2b_d1 gpio2_10 Driver off
0x1494 CTRL_CORE_PAD_GPMC_A21 D6 gpmc_a21 mmc2_dat6 gpmc_a15 vin2b_d2 gpio2_11 Driver off
0x1498 CTRL_CORE_PAD_GPMC_A22 C5 gpmc_a22 mmc2_dat7 gpmc_a16 vin2b_d3 gpio2_12 Driver off
0x149C CTRL_CORE_PAD_GPMC_A23 B5 gpmc_a23 mmc2_clk gpmc_a17 vin2b_d4 gpio2_13 Driver off
0x14A0 CTRL_CORE_PAD_GPMC_A24 D7 gpmc_a24 mmc2_dat0 gpmc_a18 vin2b_d5 gpio2_14 Driver off
0x14A4 CTRL_CORE_PAD_GPMC_A25 C6 gpmc_a25 mmc2_dat1 gpmc_a19 vin2b_d6 gpio2_15 Driver off
0x14A8 CTRL_CORE_PAD_GPMC_A26 A5 gpmc_a26 mmc2_dat2 gpmc_a20 vin2b_d7 gpio2_16 Driver off
0x14AC CTRL_CORE_PAD_GPMC_A27 B6 gpmc_a27 mmc2_dat3 gpmc_a21 vin2b_hsync1 gpio2_17 Driver off
0x14B0 CTRL_CORE_PAD_GPMC_CS1 A6 gpmc_cs1 mmc2_cmd gpmc_a22 vin2b_vsync1 gpio2_18 Driver off
0x14B4 CTRL_CORE_PAD_GPMC_CS0 F3 gpmc_cs0 gpio2_19 Driver off
0x14B8 CTRL_CORE_PAD_GPMC_CS2 G4 gpmc_cs2 qspi1_cs0 gpio2_20 gpmc_a23 gpmc_a13 Driver off
0x14BC CTRL_CORE_PAD_GPMC_CS3 G3 gpmc_cs3 qspi1_cs1 vin1a_clk0 vout3_clk gpmc_a1 gpio2_21 gpmc_a24 gpmc_a14 Driver off
0x14C0 CTRL_CORE_PAD_GPMC_CLK L4 gpmc_clk gpmc_cs7 clkout1 gpmc_wait1 vin2b_clk1 timer4 i2c3_scl dma_evt1 gpio2_22 gpmc_a20 Driver off
0x14C4 CTRL_CORE_PAD_GPMC_ADVN_ALE H5 gpmc_advn_ale gpmc_cs6 clkout2 gpmc_wait1 gpmc_a2 gpmc_a23 timer3 i2c3_sda dma_evt2 gpio2_23 gpmc_a19 Driver off
0x14C8 CTRL_CORE_PAD_GPMC_OEN_REN G5 gpmc_oen_ren gpio2_24 Driver off
0x14CC CTRL_CORE_PAD_GPMC_WEN G6 gpmc_wen gpio2_25 Driver off
0x14D0 CTRL_CORE_PAD_GPMC_BEN0 H2 gpmc_ben0 gpmc_cs4 vin2b_de1 timer2 dma_evt3 gpio2_26 gpmc_a21 Driver off
0x14D4 CTRL_CORE_PAD_GPMC_BEN1 H6 gpmc_ben1 gpmc_cs5 vin2b_clk1 gpmc_a3 vin2b_fld1 timer1 dma_evt4 gpio2_27 gpmc_a22 Driver off
0x14D8 CTRL_CORE_PAD_GPMC_WAIT0 F6 gpmc_wait0 gpio2_28 gpmc_a25 gpmc_a15 Driver off
0x1554 CTRL_CORE_PAD_VIN2A_CLK0 D8 vin2a_clk0 vout2_fld emu5 kbd_row0 eQEP1A_in pr1_edio_data_in0 pr1_edio_data_out0 gpio3_28 gpmc_a27 gpmc_a17 Driver off
0x1558 CTRL_CORE_PAD_VIN2A_DE0 B7 vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 vout2_de emu6 kbd_row1 eQEP1B_in pr1_edio_data_in1 pr1_edio_data_out1 gpio3_29 Driver off
0x155C CTRL_CORE_PAD_VIN2A_FLD0 C7 vin2a_fld0 vin2b_clk1 vout2_clk emu7 eQEP1_index pr1_edio_data_in2 pr1_edio_data_out2 gpio3_30 gpmc_a27 gpmc_a18 Driver off
0x1560 CTRL_CORE_PAD_VIN2A_HSYNC0 E8 vin2a_hsync0 vin2b_hsync1 vout2_hsync emu8 uart9_rxd spi4_sclk kbd_row2 eQEP1_strobe pr1_uart0_cts_n pr1_edio_data_in3 pr1_edio_data_out3 gpio3_31 gpmc_a27 Driver off
0x1564 CTRL_CORE_PAD_VIN2A_VSYNC0 B8 vin2a_vsync0 vin2b_vsync1 vout2_vsync emu9 uart9_txd spi4_d1 kbd_row3 ehrpwm1A pr1_uart0_rts_n pr1_edio_data_in4 pr1_edio_data_out4 gpio4_0 Driver off
0x1568 CTRL_CORE_PAD_VIN2A_D0 C8 vin2a_d0 vout2_d23 emu10 uart9_ctsn spi4_d0 kbd_row4 ehrpwm1B pr1_uart0_rxd pr1_edio_data_in5 pr1_edio_data_out5 gpio4_1 Driver off
0x156C CTRL_CORE_PAD_VIN2A_D1 B9 vin2a_d1 vout2_d22 emu11 uart9_rtsn spi4_cs0 kbd_row5 ehrpwm1_tripzone_input pr1_uart0_txd pr1_edio_data_in6 pr1_edio_data_out6 gpio4_2 Driver off
0x1570 CTRL_CORE_PAD_VIN2A_D2 A7 vin2a_d2 vout2_d21 emu12 uart10_rxd kbd_row6 eCAP1_in_PWM1_out pr1_ecap0_ecap_capin_apwm_o pr1_edio_data_in7 pr1_edio_data_out7 gpio4_3 Driver off
0x1574 CTRL_CORE_PAD_VIN2A_D3 A9 vin2a_d3 vout2_d20 emu13 uart10_txd kbd_col0 ehrpwm1_synci pr1_edc_latch0_in pr1_pru1_gpi0 pr1_pru1_gpo0 gpio4_4 Driver off
0x1578 CTRL_CORE_PAD_VIN2A_D4 A8 vin2a_d4 vout2_d19 emu14 uart10_ctsn kbd_col1 ehrpwm1_synco pr1_edc_sync0_out pr1_pru1_gpi1 pr1_pru1_gpo1 gpio4_5 Driver off
0x157C CTRL_CORE_PAD_VIN2A_D5 A11 vin2a_d5 vout2_d18 emu15 uart10_rtsn kbd_col2 eQEP2A_in pr1_edio_sof pr1_pru1_gpi2 pr1_pru1_gpo2 gpio4_6 Driver off
0x1580 CTRL_CORE_PAD_VIN2A_D6 F10 vin2a_d6 vout2_d17 emu16 mii1_rxd1 kbd_col3 eQEP2B_in pr1_mii_mt1_clk pr1_pru1_gpi3 pr1_pru1_gpo3 gpio4_7 Driver off
0x1584 CTRL_CORE_PAD_VIN2A_D7 A10 vin2a_d7 vout2_d16 emu17 mii1_rxd2 kbd_col4 eQEP2_index pr1_mii1_txen pr1_pru1_gpi4 pr1_pru1_gpo4 gpio4_8 Driver off
0x1588 CTRL_CORE_PAD_VIN2A_D8 B10 vin2a_d8 vout2_d15 emu18 mii1_rxd3 kbd_col5 eQEP2_strobe pr1_mii1_txd3 pr1_pru1_gpi5 pr1_pru1_gpo5 gpio4_9 gpmc_a26 Driver off
0x158C CTRL_CORE_PAD_VIN2A_D9 E10 vin2a_d9 vout2_d14 emu19 mii1_rxd0 kbd_col6 ehrpwm2A pr1_mii1_txd2 pr1_pru1_gpi6 pr1_pru1_gpo6 gpio4_10 gpmc_a25 Driver off
0x1590 CTRL_CORE_PAD_VIN2A_D10 D10 vin2a_d10 mdio_mclk vout2_d13 kbd_col7 ehrpwm2B pr1_mdio_mdclk pr1_pru1_gpi7 pr1_pru1_gpo7 gpio4_11 gpmc_a24 Driver off
0x1594 CTRL_CORE_PAD_VIN2A_D11 C10 vin2a_d11 mdio_d vout2_d12 kbd_row7 ehrpwm2_tripzone_input pr1_mdio_data pr1_pru1_gpi8 pr1_pru1_gpo8 gpio4_12 gpmc_a23 Driver off
0x1598 CTRL_CORE_PAD_VIN2A_D12 B11 vin2a_d12 rgmii1_txc vout2_d11 mii1_rxclk kbd_col8 eCAP2_in_PWM2_out pr1_mii1_txd1 pr1_pru1_gpi9 pr1_pru1_gpo9 gpio4_13 Driver off
0x159C CTRL_CORE_PAD_VIN2A_D13 D11 vin2a_d13 rgmii1_txctl vout2_d10 mii1_rxdv kbd_row8 eQEP3A_in pr1_mii1_txd0 pr1_pru1_gpi10 pr1_pru1_gpo10 gpio4_14 Driver off
0x15A0 CTRL_CORE_PAD_VIN2A_D14 C11 vin2a_d14 rgmii1_txd3 vout2_d9 mii1_txclk eQEP3B_in pr1_mii_mr1_clk pr1_pru1_gpi11 pr1_pru1_gpo11 gpio4_15 Driver off
0x15A4 CTRL_CORE_PAD_VIN2A_D15 B12 vin2a_d15 rgmii1_txd2 vout2_d8 mii1_txd0 eQEP3_index pr1_mii1_rxdv pr1_pru1_gpi12 pr1_pru1_gpo12 gpio4_16 Driver off
0x15A8 CTRL_CORE_PAD_VIN2A_D16 A12 vin2a_d16 vin2b_d7 rgmii1_txd1 vout2_d7 mii1_txd1 eQEP3_strobe pr1_mii1_rxd3 pr1_pru1_gpi13 pr1_pru1_gpo13 gpio4_24 Driver off
0x15AC CTRL_CORE_PAD_VIN2A_D17 A13 vin2a_d17 vin2b_d6 rgmii1_txd0 vout2_d6 mii1_txd2 ehrpwm3A pr1_mii1_rxd2 pr1_pru1_gpi14 pr1_pru1_gpo14 gpio4_25 Driver off
0x15B0 CTRL_CORE_PAD_VIN2A_D18 E11 vin2a_d18 vin2b_d5 rgmii1_rxc vout2_d5 mii1_txd3 ehrpwm3B pr1_mii1_rxd1 pr1_pru1_gpi15 pr1_pru1_gpo15 gpio4_26 Driver off
0x15B4 CTRL_CORE_PAD_VIN2A_D19 F11 vin2a_d19 vin2b_d4 rgmii1_rxctl vout2_d4 mii1_txer ehrpwm3_tripzone_input pr1_mii1_rxd0 pr1_pru1_gpi16 pr1_pru1_gpo16 gpio4_27 Driver off
0x15B8 CTRL_CORE_PAD_VIN2A_D20 B13 vin2a_d20 vin2b_d3 rgmii1_rxd3 vout2_d3 mii1_rxer eCAP3_in_PWM3_out pr1_mii1_rxer pr1_pru1_gpi17 pr1_pru1_gpo17 gpio4_28 Driver off
0x15BC CTRL_CORE_PAD_VIN2A_D21 E13 vin2a_d21 vin2b_d2 rgmii1_rxd2 vout2_d2 mii1_col pr1_mii1_rxlink pr1_pru1_gpi18 pr1_pru1_gpo18 gpio4_29 Driver off
0x15C0 CTRL_CORE_PAD_VIN2A_D22 C13 vin2a_d22 vin2b_d1 rgmii1_rxd1 vout2_d1 mii1_crs pr1_mii1_col pr1_pru1_gpi19 pr1_pru1_gpo19 gpio4_30 Driver off
0x15C4 CTRL_CORE_PAD_VIN2A_D23 D13 vin2a_d23 vin2b_d0 rgmii1_rxd0 vout2_d0 mii1_txen pr1_mii1_crs pr1_pru1_gpi20 pr1_pru1_gpo20 gpio4_31 Driver off
0x15E4 CTRL_CORE_PAD_VOUT1_D2 E14 emu2
0x1604 CTRL_CORE_PAD_VOUT1_D10 F14 emu3
0x1624 CTRL_CORE_PAD_VOUT1_D18 F13 emu4
0x163C CTRL_CORE_PAD_MDIO_MCLK L5 mdio_mclk uart3_rtsn mii0_col vin2a_clk0 vin1b_clk1 pr1_mii0_col pr2_pru1_gpi0 pr2_pru1_gpo0 gpio5_15 Driver off
0x1640 CTRL_CORE_PAD_MDIO_D L6 mdio_d uart3_ctsn mii0_txer vin2a_d0 vin1b_d0 pr1_mii0_rxlink pr2_pru1_gpi1 pr2_pru1_gpo1 gpio5_16 Driver off
0x1644 CTRL_CORE_PAD_RMII_MHZ_50_CLK P5 RMII_MHZ_50_CLK vin2a_d11 pr2_pru1_gpi2 pr2_pru1_gpo2 gpio5_17 Driver off
0x1648 CTRL_CORE_PAD_UART3_RXD N5 uart3_rxd rmii1_crs mii0_rxdv vin2a_d1 vin1b_d1 spi3_sclk pr1_mii0_rxdv pr2_pru1_gpi3 pr2_pru1_gpo3 gpio5_18 Driver off
0x164C CTRL_CORE_PAD_UART3_TXD N6 uart3_txd rmii1_rxer mii0_rxclk vin2a_d2 vin1b_d2 spi3_d1 spi4_cs1 pr1_mii_mr0_clk pr2_pru1_gpi4 pr2_pru1_gpo4 gpio5_19 Driver off
0x1650 CTRL_CORE_PAD_RGMII0_TXC T4 rgmii0_txc uart3_ctsn rmii1_rxd1 mii0_rxd3 vin2a_d3 vin1b_d3 usb3_ulpi_clk spi3_d0 spi4_cs2 pr1_mii0_rxd3 pr2_pru1_gpi5 pr2_pru1_gpo5 gpio5_20 Driver off
0x1654 CTRL_CORE_PAD_RGMII0_TXCTL T5 rgmii0_txctl uart3_rtsn rmii1_rxd0 mii0_rxd2 vin2a_d4 vin1b_d4 usb3_ulpi_stp spi3_cs0 spi4_cs3 pr1_mii0_rxd2 pr2_pru1_gpi6 pr2_pru1_gpo6 gpio5_21 Driver off
0x1658 CTRL_CORE_PAD_RGMII0_TXD3 P4 rgmii0_txd3 rmii0_crs mii0_crs vin2a_de0 vin1b_de1 usb3_ulpi_dir spi4_sclk uart4_rxd pr1_mii0_crs pr2_pru1_gpi7 pr2_pru1_gpo7 gpio5_22 Driver off
0x165C CTRL_CORE_PAD_RGMII0_TXD2 P3 rgmii0_txd2 rmii0_rxer mii0_rxer vin2a_hsync0 vin1b_hsync1 usb3_ulpi_nxt spi4_d1 uart4_txd pr1_mii0_rxer pr2_pru1_gpi8 pr2_pru1_gpo8 gpio5_23 Driver off
0x1660 CTRL_CORE_PAD_RGMII0_TXD1 R2 rgmii0_txd1 rmii0_rxd1 mii0_rxd1 vin2a_vsync0 vin1b_vsync1 usb3_ulpi_d0 spi4_d0 uart4_ctsn pr1_mii0_rxd1 pr2_pru1_gpi9 pr2_pru1_gpo9 gpio5_24 Driver off
0x1664 CTRL_CORE_PAD_RGMII0_TXD0 R1 rgmii0_txd0 rmii0_rxd0 mii0_rxd0 vin2a_d10 usb3_ulpi_d1 spi4_cs0 uart4_rtsn pr1_mii0_rxd0 pr2_pru1_gpi10 pr2_pru1_gpo10 gpio5_25 Driver off
0x1668 CTRL_CORE_PAD_RGMII0_RXC N2 rgmii0_rxc rmii1_txen mii0_txclk vin2a_d5 vin1b_d5 usb3_ulpi_d2 pr1_mii_mt0_clk pr2_pru1_gpi11 pr2_pru1_gpo11 gpio5_26 Driver off
0x166C CTRL_CORE_PAD_RGMII0_RXCTL P2 rgmii0_rxctl rmii1_txd1 mii0_txd3 vin2a_d6 vin1b_d6 usb3_ulpi_d3 pr1_mii0_txd3 pr2_pru1_gpi12 pr2_pru1_gpo12 gpio5_27 Driver off
0x1670 CTRL_CORE_PAD_RGMII0_RXD3 N1 rgmii0_rxd3 rmii1_txd0 mii0_txd2 vin2a_d7 vin1b_d7 usb3_ulpi_d4 pr1_mii0_txd2 pr2_pru1_gpi13 pr2_pru1_gpo13 gpio5_28 Driver off
0x1674 CTRL_CORE_PAD_RGMII0_RXD2 P1 rgmii0_rxd2 rmii0_txen mii0_txen vin2a_d8 usb3_ulpi_d5 pr1_mii0_txen pr2_pru1_gpi14 pr2_pru1_gpo14 gpio5_29 Driver off
0x1678 CTRL_CORE_PAD_RGMII0_RXD1 N3 rgmii0_rxd1 rmii0_txd1 mii0_txd1 vin2a_d9 usb3_ulpi_d6 pr1_mii0_txd1 pr2_pru1_gpi15 pr2_pru1_gpo15 gpio5_30 Driver off
0x167C CTRL_CORE_PAD_RGMII0_RXD0 N4 rgmii0_rxd0 rmii0_txd0 mii0_txd0 vin2a_fld0 vin1b_fld1 usb3_ulpi_d7 pr1_mii0_txd0 pr2_pru1_gpi16 pr2_pru1_gpo16 gpio5_31 Driver off
0x1680 CTRL_CORE_PAD_USB1_DRVVBUS AD3 usb1_drvvbus timer16 gpio6_12 Driver off
0x1684 CTRL_CORE_PAD_USB2_DRVVBUS AA6 usb2_drvvbus timer15 gpio6_13 Driver off
0x1688 CTRL_CORE_PAD_GPIO6_14 H21 gpio6_14 mcasp1_axr8 dcan2_tx uart10_rxd i2c3_sda timer1 gpio6_14 Driver off
0x168C CTRL_CORE_PAD_GPIO6_15 K22 gpio6_15 mcasp1_axr9 dcan2_rx uart10_txd i2c3_scl timer2 gpio6_15 Driver off
0x1690 CTRL_CORE_PAD_GPIO6_16 K23 gpio6_16 mcasp1_axr10 clkout1 timer3 gpio6_16 Driver off
0x1694 CTRL_CORE_PAD_XREF_CLK0 J25 xref_clk0 mcasp2_axr8 mcasp1_axr4 mcasp1_ahclkx mcasp5_ahclkx atl_clk0 vin1a_d0 hdq0 clkout2 timer13 pr2_mii1_col pr2_pru1_gpi5 pr2_pru1_gpo5 gpio6_17 Driver off
0x1698 CTRL_CORE_PAD_XREF_CLK1 J24 xref_clk1 mcasp2_axr9 mcasp1_axr5 mcasp2_ahclkx mcasp6_ahclkx atl_clk1 vin1a_clk0 timer14 pr2_mii1_crs pr2_pru1_gpi6 pr2_pru1_gpo6 gpio6_18 Driver off
0x169C CTRL_CORE_PAD_XREF_CLK2 H24 xref_clk2 mcasp2_axr10 mcasp1_axr6 mcasp3_ahclkx mcasp7_ahclkx atl_clk2 timer15 gpio6_19 Driver off
0x16A0 CTRL_CORE_PAD_XREF_CLK3 H25 xref_clk3 mcasp2_axr11 mcasp1_axr7 mcasp4_ahclkx mcasp8_ahclkx atl_clk3 hdq0 clkout3 timer16 gpio6_20 Driver off
0x16A4 CTRL_CORE_PAD_MCASP1_ACLKX C16 mcasp1_aclkx vin1a_fld0 i2c3_sda pr2_mdio_mdclk pr2_pru1_gpi7 pr2_pru1_gpo7 gpio7_31 Driver off
0x16A8 CTRL_CORE_PAD_MCASP1_FSX C17 mcasp1_fsx vin1a_de0 i2c3_scl pr2_mdio_data gpio7_30 Driver off
0x16AC CTRL_CORE_PAD_MCASP1_ACLKR D16 mcasp1_aclkr mcasp7_axr2 i2c4_sda gpio5_0 Driver off
0x16B0 CTRL_CORE_PAD_MCASP1_FSR D17 mcasp1_fsr mcasp7_axr3 i2c4_scl gpio5_1 Driver off
0x16B4 CTRL_CORE_PAD_MCASP1_AXR0 D14 mcasp1_axr0 uart6_rxd vin1a_vsync0 i2c5_sda pr2_mii0_rxer pr2_pru1_gpi8 pr2_pru1_gpo8 gpio5_2 Driver off
0x16B8 CTRL_CORE_PAD_MCASP1_AXR1 B14 mcasp1_axr1 uart6_txd vin1a_hsync0 i2c5_scl pr2_mii_mt0_clk pr2_pru1_gpi9 pr2_pru1_gpo9 gpio5_3 Driver off
0x16BC CTRL_CORE_PAD_MCASP1_AXR2 C14 mcasp1_axr2 mcasp6_axr2 uart6_ctsn gpio5_4 Driver off
0x16C0 CTRL_CORE_PAD_MCASP1_AXR3 B15 mcasp1_axr3 mcasp6_axr3 uart6_rtsn gpio5_5 Driver off
0x16C4 CTRL_CORE_PAD_MCASP1_AXR4 A15 mcasp1_axr4 mcasp4_axr2 gpio5_6 Driver off
0x16C8 CTRL_CORE_PAD_MCASP1_AXR5 A14 mcasp1_axr5 mcasp4_axr3 gpio5_7 Driver off
0x16CC CTRL_CORE_PAD_MCASP1_AXR6 A17 mcasp1_axr6 mcasp5_axr2 gpio5_8 Driver off
0x16D0 CTRL_CORE_PAD_MCASP1_AXR7 A16 mcasp1_axr7 mcasp5_axr3 timer4 gpio5_9 Driver off
0x16D4 CTRL_CORE_PAD_MCASP1_AXR8 A18 mcasp1_axr8 mcasp6_axr0 spi3_sclk vin1a_d15 timer5 pr2_mii0_txen pr2_pru1_gpi10 pr2_pru1_gpo10 gpio5_10 Driver off
0x16D8 CTRL_CORE_PAD_MCASP1_AXR9 B17 mcasp1_axr9 mcasp6_axr1 spi3_d1 vin1a_d14 timer6 pr2_mii0_txd3 pr2_pru1_gpi11 pr2_pru1_gpo11 gpio5_11 Driver off
0x16DC CTRL_CORE_PAD_MCASP1_AXR10 B16 mcasp1_axr10 mcasp6_aclkx mcasp6_aclkr spi3_d0 vin1a_d13 timer7 pr2_mii0_txd2 pr2_pru1_gpi12 pr2_pru1_gpo12 gpio5_12 Driver off
0x16E0 CTRL_CORE_PAD_MCASP1_AXR11 B18 mcasp1_axr11 mcasp6_fsx mcasp6_fsr spi3_cs0 vin1a_d12 timer8 pr2_mii0_txd1 pr2_pru1_gpi13 pr2_pru1_gpo13 gpio4_17 Driver off
0x16E4 CTRL_CORE_PAD_MCASP1_AXR12 A19 mcasp1_axr12 mcasp7_axr0 spi3_cs1 vin1a_d11 timer9 pr2_mii0_txd0 pr2_pru1_gpi14 pr2_pru1_gpo14 gpio4_18 Driver off
0x16E8 CTRL_CORE_PAD_MCASP1_AXR13 E17 mcasp1_axr13 mcasp7_axr1 vin1a_d10 timer10 pr2_mii_mr0_clk pr2_pru1_gpi15 pr2_pru1_gpo15 gpio6_4 Driver off
0x16EC CTRL_CORE_PAD_MCASP1_AXR14 E16 mcasp1_axr14 mcasp7_aclkx mcasp7_aclkr vin1a_d9 timer11 pr2_mii0_rxdv pr2_pru1_gpi16 pr2_pru1_gpo16 gpio6_5 Driver off
0x16F0 CTRL_CORE_PAD_MCASP1_AXR15 F16 mcasp1_axr15 mcasp7_fsx mcasp7_fsr vin1a_d8 timer12 pr2_mii0_rxd3 pr2_pru0_gpi20 pr2_pru0_gpo20 gpio6_6 Driver off
0x16F4 CTRL_CORE_PAD_MCASP2_ACLKX E19 mcasp2_aclkx vin1a_d7 pr2_mii0_rxd2 pr2_pru0_gpi18 pr2_pru0_gpo18 Driver off
0x16F8 CTRL_CORE_PAD_MCASP2_FSX D19 mcasp2_fsx vin1a_d6 pr2_mii0_rxd1 pr2_pru0_gpi19 pr2_pru0_gpo19 Driver off
0x1704 CTRL_CORE_PAD_MCASP2_AXR0 A20 mcasp2_axr0 Driver off
0x1708 CTRL_CORE_PAD_MCASP2_AXR1 B19 mcasp2_axr1 Driver off
0x170C CTRL_CORE_PAD_MCASP2_AXR2 A21 mcasp2_axr2 mcasp3_axr2 vin1a_d5 pr2_mii0_rxd0 pr2_pru0_gpi16 pr2_pru0_gpo16 gpio6_8 Driver off
0x1710 CTRL_CORE_PAD_MCASP2_AXR3 B21 mcasp2_axr3 mcasp3_axr3 vin1a_d4 pr2_mii0_rxlink pr2_pru0_gpi17 pr2_pru0_gpo17 gpio6_9 Driver off
0x1714 CTRL_CORE_PAD_MCASP2_AXR4 B20 mcasp2_axr4 mcasp8_axr0 gpio1_4 Driver off
0x1718 CTRL_CORE_PAD_MCASP2_AXR5 C19 mcasp2_axr5 mcasp8_axr1 gpio6_7 Driver off
0x171C CTRL_CORE_PAD_MCASP2_AXR6 D20 mcasp2_axr6 mcasp8_aclkx mcasp8_aclkr gpio2_29 Driver off
0x1720 CTRL_CORE_PAD_MCASP2_AXR7 C20 mcasp2_axr7 mcasp8_fsx mcasp8_fsr gpio1_5 Driver off
0x1724 CTRL_CORE_PAD_MCASP3_ACLKX A22 mcasp3_aclkx mcasp3_aclkr mcasp2_axr12 uart7_rxd vin1a_d3 pr2_mii0_crs pr2_pru0_gpi12 pr2_pru0_gpo12 gpio5_13 Driver off
0x1728 CTRL_CORE_PAD_MCASP3_FSX A23 mcasp3_fsx mcasp3_fsr mcasp2_axr13 uart7_txd vin1a_d2 pr2_mii0_col pr2_pru0_gpi13 pr2_pru0_gpo13 gpio5_14 Driver off
0x172C CTRL_CORE_PAD_MCASP3_AXR0 B22 mcasp3_axr0 mcasp2_axr14 uart7_ctsn uart5_rxd vin1a_d1 pr2_mii1_rxer pr2_pru0_gpi14 pr2_pru0_gpo14 Driver off
0x1730 CTRL_CORE_PAD_MCASP3_AXR1 B23 mcasp3_axr1 mcasp2_axr15 uart7_rtsn uart5_txd vin1a_d0 pr2_mii1_rxlink pr2_pru0_gpi15 pr2_pru0_gpo15 Driver off
0x1734 CTRL_CORE_PAD_MCASP4_ACLKX C23 mcasp4_aclkx mcasp4_aclkr spi3_sclk uart8_rxd i2c4_sda Driver off
0x1738 CTRL_CORE_PAD_MCASP4_FSX B25 mcasp4_fsx mcasp4_fsr spi3_d1 uart8_txd i2c4_scl Driver off
0x173C CTRL_CORE_PAD_MCASP4_AXR0 A24 mcasp4_axr0 spi3_d0 uart8_ctsn uart4_rxd i2c6_scl Driver off
0x1740 CTRL_CORE_PAD_MCASP4_AXR1 D23 mcasp4_axr1 spi3_cs0 uart8_rtsn uart4_txd pr2_pru1_gpi0 pr2_pru1_gpo0 i2c6_sda Driver off
0x1744 CTRL_CORE_PAD_MCASP5_ACLKX AC3 mcasp5_aclkx mcasp5_aclkr spi4_sclk uart9_rxd i2c5_sda mlb_clk pr2_pru1_gpi1 pr2_pru1_gpo1 Driver off
0x1748 CTRL_CORE_PAD_MCASP5_FSX U6 mcasp5_fsx mcasp5_fsr spi4_d1 uart9_txd i2c5_scl pr2_pru1_gpi2 pr2_pru1_gpo2 Driver off
0x174C CTRL_CORE_PAD_MCASP5_AXR0 AA5 mcasp5_axr0 spi4_d0 uart9_ctsn uart3_rxd mlb_sig pr2_mdio_mdclk pr2_pru1_gpi3 pr2_pru1_gpo3 Driver off
0x1750 CTRL_CORE_PAD_MCASP5_AXR1 AC4 mcasp5_axr1 spi4_cs0 uart9_rtsn uart3_txd mlb_dat pr2_mdio_data pr2_pru1_gpi4 pr2_pru1_gpo4 Driver off
0x1754 CTRL_CORE_PAD_MMC1_CLK U3 mmc1_clk gpio6_21 Driver off
0x1758 CTRL_CORE_PAD_MMC1_CMD V4 mmc1_cmd gpio6_22 Driver off
0x175C CTRL_CORE_PAD_MMC1_DAT0 V3 mmc1_dat0 gpio6_23 Driver off
0x1760 CTRL_CORE_PAD_MMC1_DAT1 V2 mmc1_dat1 gpio6_24 Driver off
0x1764 CTRL_CORE_PAD_MMC1_DAT2 W1 mmc1_dat2 gpio6_25 Driver off
0x1768 CTRL_CORE_PAD_MMC1_DAT3 V1 mmc1_dat3 gpio6_26 Driver off
0x176C CTRL_CORE_PAD_MMC1_SDCD U5 mmc1_sdcd uart6_rxd i2c4_sda gpio6_27 Driver off
0x1770 CTRL_CORE_PAD_MMC1_SDWP V5 mmc1_sdwp uart6_txd i2c4_scl gpio6_28 Driver off
0x1774 CTRL_CORE_PAD_GPIO6_10 Y5 gpio6_10 mdio_mclk i2c3_sda usb3_ulpi_d7 vin2b_hsync1 vin1a_clk0 ehrpwm2A pr2_mii_mt1_clk pr2_pru0_gpi0 pr2_pru0_gpo0 gpio6_10 Driver off
0x1778 CTRL_CORE_PAD_GPIO6_11 Y6 gpio6_11 mdio_d i2c3_scl usb3_ulpi_d6 vin2b_vsync1 vin1a_de0 ehrpwm2B pr2_mii1_txen pr2_pru0_gpi1 pr2_pru0_gpo1 gpio6_11 Driver off
0x177C CTRL_CORE_PAD_MMC3_CLK Y2 mmc3_clk usb3_ulpi_d5 vin2b_d7 vin1a_d7 ehrpwm2_tripzone_input pr2_mii1_txd3 pr2_pru0_gpi2 pr2_pru0_gpo2 gpio6_29 Driver off
0x1780 CTRL_CORE_PAD_MMC3_CMD Y1 mmc3_cmd spi3_sclk usb3_ulpi_d4 vin2b_d6 vin1a_d6 eCAP2_in_PWM2_out pr2_mii1_txd2 pr2_pru0_gpi3 pr2_pru0_gpo3 gpio6_30 Driver off
0x1784 CTRL_CORE_PAD_MMC3_DAT0 Y4 mmc3_dat0 spi3_d1 uart5_rxd usb3_ulpi_d3 vin2b_d5 vin1a_d5 eQEP3A_in pr2_mii1_txd1 pr2_pru0_gpi4 pr2_pru0_gpo4 gpio6_31 Driver off
0x1788 CTRL_CORE_PAD_MMC3_DAT1 AA2 mmc3_dat1 spi3_d0 uart5_txd usb3_ulpi_d2 vin2b_d4 vin1a_d4 eQEP3B_in pr2_mii1_txd0 pr2_pru0_gpi5 pr2_pru0_gpo5 gpio7_0 Driver off
0x178C CTRL_CORE_PAD_MMC3_DAT2 AA3 mmc3_dat2 spi3_cs0 uart5_ctsn usb3_ulpi_d1 vin2b_d3 vin1a_d3 eQEP3_index pr2_mii_mr1_clk pr2_pru0_gpi6 pr2_pru0_gpo6 gpio7_1 Driver off
0x1790 CTRL_CORE_PAD_MMC3_DAT3 W2 mmc3_dat3 spi3_cs1 uart5_rtsn usb3_ulpi_d0 vin2b_d2 vin1a_d2 eQEP3_strobe pr2_mii1_rxdv pr2_pru0_gpi7 pr2_pru0_gpo7 gpio7_2 Driver off
0x1794 CTRL_CORE_PAD_MMC3_DAT4 Y3 mmc3_dat4 spi4_sclk uart10_rxd usb3_ulpi_nxt vin2b_d1 vin1a_d1 ehrpwm3A pr2_mii1_rxd3 pr2_pru0_gpi8 pr2_pru0_gpo8 gpio1_22 Driver off
0x1798 CTRL_CORE_PAD_MMC3_DAT5 AA1 mmc3_dat5 spi4_d1 uart10_txd usb3_ulpi_dir vin2b_d0 vin1a_d0 ehrpwm3B pr2_mii1_rxd2 pr2_pru0_gpi9 pr2_pru0_gpo9 gpio1_23 Driver off
0x179C CTRL_CORE_PAD_MMC3_DAT6 AA4 mmc3_dat6 spi4_d0 uart10_ctsn usb3_ulpi_stp vin2b_de1 vin1a_hsync0 ehrpwm3_tripzone_input pr2_mii1_rxd1 pr2_pru0_gpi10 pr2_pru0_gpo10 gpio1_24 Driver off
0x17A0 CTRL_CORE_PAD_MMC3_DAT7 AB1 mmc3_dat7 spi4_cs0 uart10_rtsn usb3_ulpi_clk vin2b_clk1 vin1a_vsync0 eCAP3_in_PWM3_out pr2_mii1_rxd0 pr2_pru0_gpi11 pr2_pru0_gpo11 gpio1_25 Driver off
0x17A4 CTRL_CORE_PAD_SPI1_SCLK C24 spi1_sclk gpio7_7 Driver off
0x17A8 CTRL_CORE_PAD_SPI1_D1 D24 spi1_d1 gpio7_8 Driver off
0x17AC CTRL_CORE_PAD_SPI1_D0 D25 spi1_d0 gpio7_9 Driver off
0x17B0 CTRL_CORE_PAD_SPI1_CS0 B24 spi1_cs0 gpio7_10 Driver off
0x17B4 CTRL_CORE_PAD_SPI1_CS1 C25 spi1_cs1 spi2_cs1 gpio7_11 Driver off
0x17B8 CTRL_CORE_PAD_SPI1_CS2 E24 spi1_cs2 uart4_rxd mmc3_sdcd spi2_cs2 dcan2_tx mdio_mclk hdmi1_hpd gpio7_12 Driver off
0x17BC CTRL_CORE_PAD_SPI1_CS3 E25 spi1_cs3 uart4_txd mmc3_sdwp spi2_cs3 dcan2_rx mdio_d hdmi1_cec gpio7_13 Driver off
0x17C0 CTRL_CORE_PAD_SPI2_SCLK G25 spi2_sclk uart3_rxd gpio7_14 Driver off
0x17C4 CTRL_CORE_PAD_SPI2_D1 F25 spi2_d1 uart3_txd gpio7_15 Driver off
0x17C8 CTRL_CORE_PAD_SPI2_D0 G24 spi2_d0 uart3_ctsn uart5_rxd gpio7_16 Driver off
0x17CC CTRL_CORE_PAD_SPI2_CS0 F24 spi2_cs0 uart3_rtsn uart5_txd gpio7_17 Driver off
0x17D0 CTRL_CORE_PAD_DCAN1_TX H22 dcan1_tx uart8_rxd mmc2_sdcd hdmi1_hpd gpio1_14 Driver off
0x17D4 CTRL_CORE_PAD_DCAN1_RX H23 dcan1_rx uart8_txd mmc2_sdwp hdmi1_cec gpio1_15 Driver off
0x17E0 CTRL_CORE_PAD_UART1_RXD L25 uart1_rxd mmc4_sdcd gpio7_22 Driver off
0x17E4 CTRL_CORE_PAD_UART1_TXD M25 uart1_txd mmc4_sdwp gpio7_23 Driver off
0x17E8 CTRL_CORE_PAD_UART1_CTSN L20 uart1_ctsn uart9_rxd mmc4_clk gpio7_24 Driver off
0x17EC CTRL_CORE_PAD_UART1_RTSN M24 uart1_rtsn uart9_txd mmc4_cmd gpio7_25 Driver off
0x17F0 CTRL_CORE_PAD_UART2_RXD N23 uart2_rxd uart3_ctsn uart3_rctx mmc4_dat0 uart2_rxd uart1_dcdn gpio7_26 Driver off
0x17F4 CTRL_CORE_PAD_UART2_TXD N25 uart2_txd uart3_rtsn uart3_sd mmc4_dat1 uart2_txd uart1_dsrn gpio7_27 Driver off
0x17F8 CTRL_CORE_PAD_UART2_CTSN N22 uart2_ctsn uart3_rxd mmc4_dat2 uart10_rxd uart1_dtrn gpio1_16 Driver off
0x17FC CTRL_CORE_PAD_UART2_RTSN N24 uart2_rtsn uart3_txd uart3_irtx mmc4_dat3 uart10_txd uart1_rin gpio1_17 Driver off
0x1800 CTRL_CORE_PAD_I2C1_SDA G23 i2c1_sda Driver off
0x1804 CTRL_CORE_PAD_I2C1_SCL G22 i2c1_scl Driver off
0x1808 CTRL_CORE_PAD_I2C2_SDA F23 i2c2_sda hdmi1_ddc_scl Driver off
0x180C CTRL_CORE_PAD_I2C2_SCL G21 i2c2_scl hdmi1_ddc_sda Driver off
0x1818 CTRL_CORE_PAD_WAKEUP0 AC10 dcan1_rx gpio1_0 sys_nirq2 Driver off
0x1824 CTRL_CORE_PAD_WAKEUP3 AB10 sys_nirq1 gpio1_3 dcan2_rx Driver off
0x1830 CTRL_CORE_PAD_TMS L21 tms
0x1834 CTRL_CORE_PAD_TDI L23 tdi gpio8_27
0x1838 CTRL_CORE_PAD_TDO J20 tdo gpio8_28
0x183C CTRL_CORE_PAD_TCLK K21 tclk
0x1840 CTRL_CORE_PAD_TRSTN L22 trstn
0x1844 CTRL_CORE_PAD_RTCK K25 rtck gpio8_29
0x1848 CTRL_CORE_PAD_EMU0 C21 emu0 gpio8_30
0x184C CTRL_CORE_PAD_EMU1 C22 emu1 gpio8_31
0x185C CTRL_CORE_PAD_RESETN K24 resetn
0x1860 CTRL_CORE_PAD_NMIN_DSP L24 nmin_dsp
0x1864 CTRL_CORE_PAD_RSTOUTN E20 rstoutn
  1. NA in table stands for Not Applicable.