SPRS960G June   2016  – November 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IVA
    6. 6.6  IPU
    7. 6.7  GPU
    8. 6.8  BB2D
    9. 6.9  PRU-ICSS
    10. 6.10 Memory Subsystem
      1. 6.10.1 EMIF
      2. 6.10.2 GPMC
      3. 6.10.3 ELM
      4. 6.10.4 OCMC
    11. 6.11 Interprocessor Communication
      1. 6.11.1 MailBox
      2. 6.11.2 Spinlock
    12. 6.12 Interrupt Controller
    13. 6.13 EDMA
    14. 6.14 Peripherals
      1. 6.14.1  VIP
      2. 6.14.2  DSS
      3. 6.14.3  Timers
        1. 6.14.3.1 General-Purpose Timers
        2. 6.14.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.14.3.3 Watchdog Timer
      4. 6.14.4  I2C
      5. 6.14.5  UART
        1. 6.14.5.1 UART Features
        2. 6.14.5.2 IrDA Features
        3. 6.14.5.3 CIR Features
      6. 6.14.6  McSPI
      7. 6.14.7  QSPI
      8. 6.14.8  McASP
      9. 6.14.9  USB
      10. 6.14.10 PCIe
      11. 6.14.11 DCAN
      12. 6.14.12 GMAC_SW
      13. 6.14.13 eMMC/SD/SDIO
      14. 6.14.14 GPIO
      15. 6.14.15 ePWM
      16. 6.14.16 eCAP
      17. 6.14.17 eQEP
    15. 6.15 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CBD|538
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10.6.23.6 PRU-ICSS Manual Functional Mapping

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Direct Input mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-190Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode for a definition of the Manual modes.

Table 5-190 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-190 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode

BALL BALL NAME PR1_PRU1_DIR_IN_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D10 vin2a_d10 0 800 CFG_VIN2A_D10_IN pr1_pru1_gpi7
C10 vin2a_d11 0 0 CFG_VIN2A_D11_IN pr1_pru1_gpi8
B11 vin2a_d12 0 200 CFG_VIN2A_D12_IN pr1_pru1_gpi9
D11 vin2a_d13 0 0 CFG_VIN2A_D13_IN pr1_pru1_gpi10
C11 vin2a_d14 0 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11
B12 vin2a_d15 0 400 CFG_VIN2A_D15_IN pr1_pru1_gpi12
A12 vin2a_d16 0 300 CFG_VIN2A_D16_IN pr1_pru1_gpi13
A13 vin2a_d17 0 400 CFG_VIN2A_D17_IN pr1_pru1_gpi14
E11 vin2a_d18 0 900 CFG_VIN2A_D18_IN pr1_pru1_gpi15
F11 vin2a_d19 0 1500 CFG_VIN2A_D19_IN pr1_pru1_gpi16
B13 vin2a_d20 0 100 CFG_VIN2A_D20_IN pr1_pru1_gpi17
E13 vin2a_d21 0 500 CFG_VIN2A_D21_IN pr1_pru1_gpi18
C13 vin2a_d22 0 500 CFG_VIN2A_D22_IN pr1_pru1_gpi19
D13 vin2a_d23 0 600 CFG_VIN2A_D23_IN pr1_pru1_gpi20
A9 vin2a_d3 0 900 CFG_VIN2A_D3_IN pr1_pru1_gpi0
A8 vin2a_d4 0 100 CFG_VIN2A_D4_IN pr1_pru1_gpi1
A11 vin2a_d5 0 600 CFG_VIN2A_D5_IN pr1_pru1_gpi2
F10 vin2a_d6 0 200 CFG_VIN2A_D6_IN pr1_pru1_gpi3
A10 vin2a_d7 0 400 CFG_VIN2A_D7_IN pr1_pru1_gpi4
B10 vin2a_d8 0 500 CFG_VIN2A_D8_IN pr1_pru1_gpi5
E10 vin2a_d9 0 600 CFG_VIN2A_D9_IN pr1_pru1_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Direct Output mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-191Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode for a definition of the Manual modes.

Table 5-191 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-191 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode

BALL BALL NAME PR1_PRU1_DIR_OUT_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
D10 vin2a_d10 0 1000 CFG_VIN2A_D10_OUT pr1_pru1_gpo7
C10 vin2a_d11 0 1300 CFG_VIN2A_D11_OUT pr1_pru1_gpo8
B11 vin2a_d12 0 2300 CFG_VIN2A_D12_OUT pr1_pru1_gpo9
D11 vin2a_d13 0 2200 CFG_VIN2A_D13_OUT pr1_pru1_gpo10
C11 vin2a_d14 0 1800 CFG_VIN2A_D14_OUT pr1_pru1_gpo11
B12 vin2a_d15 0 1800 CFG_VIN2A_D15_OUT pr1_pru1_gpo12
A12 vin2a_d16 0 1600 CFG_VIN2A_D16_OUT pr1_pru1_gpo13
A13 vin2a_d17 0 2000 CFG_VIN2A_D17_OUT pr1_pru1_gpo14
E11 vin2a_d18 0 700 CFG_VIN2A_D18_OUT pr1_pru1_gpo15
F11 vin2a_d19 0 700 CFG_VIN2A_D19_OUT pr1_pru1_gpo16
B13 vin2a_d20 0 500 CFG_VIN2A_D20_OUT pr1_pru1_gpo17
E13 vin2a_d21 0 400 CFG_VIN2A_D21_OUT pr1_pru1_gpo18
C13 vin2a_d22 0 0 CFG_VIN2A_D22_OUT pr1_pru1_gpo19
D13 vin2a_d23 0 400 CFG_VIN2A_D23_OUT pr1_pru1_gpo20
A9 vin2a_d3 0 2200 CFG_VIN2A_D3_OUT pr1_pru1_gpo0
A8 vin2a_d4 540 2800 CFG_VIN2A_D4_OUT pr1_pru1_gpo1
A11 vin2a_d5 0 400 CFG_VIN2A_D5_OUT pr1_pru1_gpo2
F10 vin2a_d6 0 1500 CFG_VIN2A_D6_OUT pr1_pru1_gpo3
A10 vin2a_d7 0 2200 CFG_VIN2A_D7_OUT pr1_pru1_gpo4
B10 vin2a_d8 0 2600 CFG_VIN2A_D8_OUT pr1_pru1_gpo5
E10 vin2a_d9 0 2300 CFG_VIN2A_D9_OUT pr1_pru1_gpo6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Parallel Capture Mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-192Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture Mode for a definition of the Manual modes.

Table 5-192 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-192 Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture Mode

BALL BALL NAME PR1_PRU1_PAR_CAP_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D10 vin2a_d10 1535 0 CFG_VIN2A_D10_IN pr1_pru1_gpi7
C10 vin2a_d11 1151 0 CFG_VIN2A_D11_IN pr1_pru1_gpi8
B11 vin2a_d12 1173 0 CFG_VIN2A_D12_IN pr1_pru1_gpi9
D11 vin2a_d13 970 0 CFG_VIN2A_D13_IN pr1_pru1_gpi10
C11 vin2a_d14 1196 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11
B12 vin2a_d15 1286 0 CFG_VIN2A_D15_IN pr1_pru1_gpi12
A12 vin2a_d16 1354 0 CFG_VIN2A_D16_IN pr1_pru1_gpi13
A13 vin2a_d17 1331 0 CFG_VIN2A_D17_IN pr1_pru1_gpi14
E11 vin2a_d18 2097 0 CFG_VIN2A_D18_IN pr1_pru1_gpi15
F11 vin2a_d19 0 453 CFG_VIN2A_D19_IN pr1_pru1_gpi16
A9 vin2a_d3 1566 0 CFG_VIN2A_D3_IN pr1_pru1_gpi0
A8 vin2a_d4 1012 0 CFG_VIN2A_D4_IN pr1_pru1_gpi1
A11 vin2a_d5 1337 0 CFG_VIN2A_D5_IN pr1_pru1_gpi2
F10 vin2a_d6 1130 0 CFG_VIN2A_D6_IN pr1_pru1_gpi3
A10 vin2a_d7 1202 0 CFG_VIN2A_D7_IN pr1_pru1_gpi4
B10 vin2a_d8 1395 0 CFG_VIN2A_D8_IN pr1_pru1_gpi5
E10 vin2a_d9 1338 0 CFG_VIN2A_D9_IN pr1_pru1_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Input mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-193Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode for a definition of the Manual modes.

Table 5-193 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-193 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode

BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
Y5 gpio6_10 1000 3300 CFG_GPIO6_10_IN pr2_pru0_gpi0
Y6 gpio6_11 1000 3400 CFG_GPIO6_11_IN pr2_pru0_gpi1
F16 mcasp1_axr15 0 1300 CFG_MCASP1_AXR15_IN pr2_pru0_gpi20
E19 mcasp2_aclkx 0 800 CFG_MCASP2_ACLKX_IN pr2_pru0_gpi18
A21 mcasp2_axr2 0 1900 CFG_MCASP2_AXR2_IN pr2_pru0_gpi16
B21 mcasp2_axr3 0 1400 CFG_MCASP2_AXR3_IN pr2_pru0_gpi17
D19 mcasp2_fsx 0 1400 CFG_MCASP2_FSX_IN pr2_pru0_gpi19
B22 mcasp3_axr0 0 1400 CFG_MCASP3_AXR0_IN pr2_pru0_gpi14
B23 mcasp3_axr1 0 1000 CFG_MCASP3_AXR1_IN pr2_pru0_gpi15
A23 mcasp3_fsx 0 1300 CFG_MCASP3_FSX_IN pr2_pru0_gpi13
Y2 mmc3_clk 1000 3700 CFG_MMC3_CLK_IN pr2_pru0_gpi2
Y1 mmc3_cmd 1000 3500 CFG_MMC3_CMD_IN pr2_pru0_gpi3
Y4 mmc3_dat0 1000 3500 CFG_MMC3_DAT0_IN pr2_pru0_gpi4
AA2 mmc3_dat1 1000 4000 CFG_MMC3_DAT1_IN pr2_pru0_gpi5
AA3 mmc3_dat2 1000 3300 CFG_MMC3_DAT2_IN pr2_pru0_gpi6
W2 mmc3_dat3 1000 3900 CFG_MMC3_DAT3_IN pr2_pru0_gpi7
Y3 mmc3_dat4 1000 3500 CFG_MMC3_DAT4_IN pr2_pru0_gpi8
AA1 mmc3_dat5 1000 3600 CFG_MMC3_DAT5_IN pr2_pru0_gpi9
AA4 mmc3_dat6 1000 3500 CFG_MMC3_DAT6_IN pr2_pru0_gpi10
AB1 mmc3_dat7 1000 3100 CFG_MMC3_DAT7_IN pr2_pru0_gpi11
A22 mcasp3_aclkx 0 0 CFG_MCASP3_ACLKX_IN pr2_pru0_gpi12

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Output mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-194Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode for a definition of the Manual modes.

Table 5-194 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-194 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode

BALL BALL NAME PR2_PRU0_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
Y5 gpio6_10 1800 1900 CFG_GPIO6_10_OUT pr2_pru0_gpo0
Y6 gpio6_11 2500 2100 CFG_GPIO6_11_OUT pr2_pru0_gpo1
F16 mcasp1_axr15 0 400 CFG_MCASP1_AXR15_OUT pr2_pru0_gpo20
E19 mcasp2_aclkx 0 400 CFG_MCASP2_ACLKX_OUT pr2_pru0_gpo18
A21 mcasp2_axr2 0 500 CFG_MCASP2_AXR2_OUT pr2_pru0_gpo16
B21 mcasp2_axr3 0 500 CFG_MCASP2_AXR3_OUT pr2_pru0_gpo17
D19 mcasp2_fsx 0 0 CFG_MCASP2_FSX_OUT pr2_pru0_gpo19
A22 mcasp3_aclkx 0 500 CFG_MCASP3_ACLKX_OUT pr2_pru0_gpo12
B22 mcasp3_axr0 0 0 CFG_MCASP3_AXR0_OUT pr2_pru0_gpo14
B23 mcasp3_axr1 0 200 CFG_MCASP3_AXR1_OUT pr2_pru0_gpo15
A23 mcasp3_fsx 0 300 CFG_MCASP3_FSX_OUT pr2_pru0_gpo13
Y2 mmc3_clk 2100 2200 CFG_MMC3_CLK_OUT pr2_pru0_gpo2
Y1 mmc3_cmd 2300 2300 CFG_MMC3_CMD_OUT pr2_pru0_gpo3
Y4 mmc3_dat0 2000 1600 CFG_MMC3_DAT0_OUT pr2_pru0_gpo4
AA2 mmc3_dat1 2000 1700 CFG_MMC3_DAT1_OUT pr2_pru0_gpo5
AA3 mmc3_dat2 2050 2200 CFG_MMC3_DAT2_OUT pr2_pru0_gpo6
W2 mmc3_dat3 2000 2000 CFG_MMC3_DAT3_OUT pr2_pru0_gpo7
Y3 mmc3_dat4 2150 2600 CFG_MMC3_DAT4_OUT pr2_pru0_gpo8
AA1 mmc3_dat5 2400 2600 CFG_MMC3_DAT5_OUT pr2_pru0_gpo9
AA4 mmc3_dat6 2200 2300 CFG_MMC3_DAT6_OUT pr2_pru0_gpo10
AB1 mmc3_dat7 1800 2400 CFG_MMC3_DAT7_OUT pr2_pru0_gpo11

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Input mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-195Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode for a definition of the Manual modes.

Table 5-195 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-195 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode

BALL BALL NAME PR2_PRU1_DIR_IN_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
P5 RMII_MHZ_50_CLK 1400 1200 CFG_RMII_MHZ_50_CLK_IN pr2_pru1_gpi2
L6 mdio_d 1300 1600 CFG_MDIO_D_IN pr2_pru1_gpi1
L5 mdio_mclk 1400 800 CFG_MDIO_MCLK_IN pr2_pru1_gpi0
N2 rgmii0_rxc 1400 500 CFG_RGMII0_RXC_IN pr2_pru1_gpi11
P2 rgmii0_rxctl 1400 1800 CFG_RGMII0_RXCTL_IN pr2_pru1_gpi12
N4 rgmii0_rxd0 1400 1300 CFG_RGMII0_RXD0_IN pr2_pru1_gpi16
N3 rgmii0_rxd1 1400 1650 CFG_RGMII0_RXD1_IN pr2_pru1_gpi15
P1 rgmii0_rxd2 1400 1400 CFG_RGMII0_RXD2_IN pr2_pru1_gpi14
N1 rgmii0_rxd3 1400 1650 CFG_RGMII0_RXD3_IN pr2_pru1_gpi13
T4 rgmii0_txc 1400 900 CFG_RGMII0_TXC_IN pr2_pru1_gpi5
T5 rgmii0_txctl 1400 1300 CFG_RGMII0_TXCTL_IN pr2_pru1_gpi6
R1 rgmii0_txd0 1400 900 CFG_RGMII0_TXD0_IN pr2_pru1_gpi10
R2 rgmii0_txd1 1300 1400 CFG_RGMII0_TXD1_IN pr2_pru1_gpi9
P3 rgmii0_txd2 1300 1100 CFG_RGMII0_TXD2_IN pr2_pru1_gpi8
P4 rgmii0_txd3 1300 1300 CFG_RGMII0_TXD3_IN pr2_pru1_gpi7
N5 uart3_rxd 1300 1000 CFG_UART3_RXD_IN pr2_pru1_gpi3
N6 uart3_txd 1300 800 CFG_UART3_TXD_IN pr2_pru1_gpi4

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Input mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-196Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode for a definition of the Manual modes.

Table 5-196 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-196 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode

BALL BALL NAME PR2_PRU1_DIR_IN_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
C16 mcasp1_aclkx 400 0 CFG_MCASP1_ACLKX_IN pr2_pru1_gpi7
D14 mcasp1_axr0 700 200 CFG_MCASP1_AXR0_IN pr2_pru1_gpi8
B14 mcasp1_axr1 600 300 CFG_MCASP1_AXR1_IN pr2_pru1_gpi9
B16 mcasp1_axr10 600 500 CFG_MCASP1_AXR10_IN pr2_pru1_gpi12
B18 mcasp1_axr11 700 500 CFG_MCASP1_AXR11_IN pr2_pru1_gpi13
A19 mcasp1_axr12 500 0 CFG_MCASP1_AXR12_IN pr2_pru1_gpi14
E17 mcasp1_axr13 600 200 CFG_MCASP1_AXR13_IN pr2_pru1_gpi15
E16 mcasp1_axr14 600 0 CFG_MCASP1_AXR14_IN pr2_pru1_gpi16
A18 mcasp1_axr8 800 0 CFG_MCASP1_AXR8_IN pr2_pru1_gpi10
B17 mcasp1_axr9 600 300 CFG_MCASP1_AXR9_IN pr2_pru1_gpi11
D23 mcasp4_axr1 500 0 CFG_MCASP4_AXR1_IN pr2_pru1_gpi0
AC3 mcasp5_aclkx 2100 1959 CFG_MCASP5_ACLKX_IN pr2_pru1_gpi1
AA5 mcasp5_axr0 2300 2000 CFG_MCASP5_AXR0_IN pr2_pru1_gpi3
AC4 mcasp5_axr1 2300 1800 CFG_MCASP5_AXR1_IN pr2_pru1_gpi4
U6 mcasp5_fsx 2100 1780 CFG_MCASP5_FSX_IN pr2_pru1_gpi2
J25 xref_clk0 0 0 CFG_XREF_CLK0_IN pr2_pru1_gpi5
J24 xref_clk1 0 0 CFG_XREF_CLK1_IN pr2_pru1_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Output mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-197Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode for a definition of the Manual modes.

Table 5-197 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-197 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode

BALL BALL NAME PR2_PRU1_DIR_OUT_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
P5 RMII_MHZ_50_CLK 2306 100 CFG_RMII_MHZ_50_CLK_OUT pr2_pru1_gpo2
L6 mdio_d 1900 2000 CFG_MDIO_D_OUT pr2_pru1_gpo1
L5 mdio_mclk 2000 1100 CFG_MDIO_MCLK_OUT pr2_pru1_gpo0
N2 rgmii0_rxc 2000 1200 CFG_RGMII0_RXC_OUT pr2_pru1_gpo11
P2 rgmii0_rxctl 2000 1700 CFG_RGMII0_RXCTL_OUT pr2_pru1_gpo12
N4 rgmii0_rxd0 2000 1000 CFG_RGMII0_RXD0_OUT pr2_pru1_gpo16
N3 rgmii0_rxd1 2200 1000 CFG_RGMII0_RXD1_OUT pr2_pru1_gpo15
P1 rgmii0_rxd2 2200 1300 CFG_RGMII0_RXD2_OUT pr2_pru1_gpo14
N1 rgmii0_rxd3 2250 1100 CFG_RGMII0_RXD3_OUT pr2_pru1_gpo13
T4 rgmii0_txc 2350 1000 CFG_RGMII0_TXC_OUT pr2_pru1_gpo5
T5 rgmii0_txctl 2000 1200 CFG_RGMII0_TXCTL_OUT pr2_pru1_gpo6
R1 rgmii0_txd0 2000 1500 CFG_RGMII0_TXD0_OUT pr2_pru1_gpo10
R2 rgmii0_txd1 1850 1000 CFG_RGMII0_TXD1_OUT pr2_pru1_gpo9
P3 rgmii0_txd2 2100 1100 CFG_RGMII0_TXD2_OUT pr2_pru1_gpo8
P4 rgmii0_txd3 2200 1000 CFG_RGMII0_TXD3_OUT pr2_pru1_gpo7
N5 uart3_rxd 2000 1600 CFG_UART3_RXD_OUT pr2_pru1_gpo3
N6 uart3_txd 2000 1000 CFG_UART3_TXD_OUT pr2_pru1_gpo4

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Output mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-198Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode for a definition of the Manual modes.

Table 5-198 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-198 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode

BALL BALL NAME PR2_PRU1_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
C16 mcasp1_aclkx 200 800 CFG_MCASP1_ACLKX_OUT pr2_pru1_gpo7
D14 mcasp1_axr0 200 1000 CFG_MCASP1_AXR0_OUT pr2_pru1_gpo8
B14 mcasp1_axr1 0 1110 CFG_MCASP1_AXR1_OUT pr2_pru1_gpo9
B16 mcasp1_axr10 0 2500 CFG_MCASP1_AXR10_OUT pr2_pru1_gpo12
B18 mcasp1_axr11 0 1900 CFG_MCASP1_AXR11_OUT pr2_pru1_gpo13
A19 mcasp1_axr12 0 2300 CFG_MCASP1_AXR12_OUT pr2_pru1_gpo14
E17 mcasp1_axr13 200 1200 CFG_MCASP1_AXR13_OUT pr2_pru1_gpo15
E16 mcasp1_axr14 200 1100 CFG_MCASP1_AXR14_OUT pr2_pru1_gpo16
A18 mcasp1_axr8 200 1600 CFG_MCASP1_AXR8_OUT pr2_pru1_gpo10
B17 mcasp1_axr9 0 1900 CFG_MCASP1_AXR9_OUT pr2_pru1_gpo11
D23 mcasp4_axr1 0 700 CFG_MCASP4_AXR1_OUT pr2_pru1_gpo0
AC3 mcasp5_aclkx 1400 4000 CFG_MCASP5_ACLKX_OUT pr2_pru1_gpo1
AA5 mcasp5_axr0 1500 3000 CFG_MCASP5_AXR0_OUT pr2_pru1_gpo3
AC4 mcasp5_axr1 1500 1900 CFG_MCASP5_AXR1_OUT pr2_pru1_gpo4
U6 mcasp5_fsx 1300 2700 CFG_MCASP5_FSX_OUT pr2_pru1_gpo2
J25 xref_clk0 0 160 CFG_XREF_CLK0_OUT pr2_pru1_gpo5
J24 xref_clk1 0 0 CFG_XREF_CLK1_OUT pr2_pru1_gpo6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-199Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode for a definition of the Manual modes.

Table 5-199 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-199 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode

BALL BALL NAME PR2_PRU0_PAR_CAP_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
Y5 gpio6_10 4125 481 CFG_GPIO6_10_IN pr2_pru0_gpi0
Y6 gpio6_11 3935 997 CFG_GPIO6_11_IN pr2_pru0_gpi1
A21 mcasp2_axr2 0 0 CFG_MCASP2_AXR2_IN pr2_pru0_gpi16
A22 mcasp3_aclkx 571 0 CFG_MCASP3_ACLKX_IN pr2_pru0_gpi12
B22 mcasp3_axr0 1570 0 CFG_MCASP3_AXR0_IN pr2_pru0_gpi14
B23 mcasp3_axr1 1405 0 CFG_MCASP3_AXR1_IN pr2_pru0_gpi15
A23 mcasp3_fsx 1946 0 CFG_MCASP3_FSX_IN pr2_pru0_gpi13
Y2 mmc3_clk 4093 1066 CFG_MMC3_CLK_IN pr2_pru0_gpi2
Y1 mmc3_cmd 4043 921 CFG_MMC3_CMD_IN pr2_pru0_gpi3
Y4 mmc3_dat0 4010 864 CFG_MMC3_DAT0_IN pr2_pru0_gpi4
AA2 mmc3_dat1 3817 1643 CFG_MMC3_DAT1_IN pr2_pru0_gpi5
AA3 mmc3_dat2 4040 673 CFG_MMC3_DAT2_IN pr2_pru0_gpi6
W2 mmc3_dat3 3923 1478 CFG_MMC3_DAT3_IN pr2_pru0_gpi7
Y3 mmc3_dat4 4096 729 CFG_MMC3_DAT4_IN pr2_pru0_gpi8
AA1 mmc3_dat5 3926 1271 CFG_MMC3_DAT5_IN pr2_pru0_gpi9
AA4 mmc3_dat6 4004 929 CFG_MMC3_DAT6_IN pr2_pru0_gpi10
AB1 mmc3_dat7 3963 666 CFG_MMC3_DAT7_IN pr2_pru0_gpi11

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-200Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode for a definition of the Manual modes.

Table 5-200 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-200 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode

BALL BALL NAME PR2_PRU1_PAR_CAP_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
P5 RMII_MHZ_50_CLK 1717 0 CFG_RMII_MHZ_50_CLK_IN pr2_pru1_gpi2
L5 mdio_d 2088 0 CFG_MDIO_D_IN pr2_pru1_gpi1
L6 mdio_mclk 1321 0 CFG_MDIO_MCLK_IN pr2_pru1_gpi0
N2 rgmii0_rxc 1287 0 CFG_RGMII0_RXC_IN pr2_pru1_gpi11
P2 rgmii0_rxctl 2456 0 CFG_RGMII0_RXCTL_IN pr2_pru1_gpi12
N4 rgmii0_rxd0 0 0 CFG_RGMII0_RXD0_IN pr2_pru1_gpi16
N3 rgmii0_rxd1 2157 0 CFG_RGMII0_RXD1_IN pr2_pru1_gpi15
P1 rgmii0_rxd2 2008 0 CFG_RGMII0_RXD2_IN pr2_pru1_gpi14
N1 rgmii0_rxd3 2271 0 CFG_RGMII0_RXD3_IN pr2_pru1_gpi13
T4 rgmii0_txc 1851 0 CFG_RGMII0_TXC_IN pr2_pru1_gpi5
T5 rgmii0_txctl 1875 0 CFG_RGMII0_TXCTL_IN pr2_pru1_gpi6
R1 rgmii0_txd0 1685 0 CFG_RGMII0_TXD0_IN pr2_pru1_gpi10
R2 rgmii0_txd1 2131 0 CFG_RGMII0_TXD1_IN pr2_pru1_gpi9
P3 rgmii0_txd2 1734 0 CFG_RGMII0_TXD2_IN pr2_pru1_gpi8
P4 rgmii0_txd3 1764 0 CFG_RGMII0_TXD3_IN pr2_pru1_gpi7
N5 uart3_rxd 1654 0 CFG_UART3_RXD_IN pr2_pru1_gpi3
N6 uart3_txd 1242 0 CFG_UART3_TXD_IN pr2_pru1_gpi4

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-201Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode for a definition of the Manual modes.

Table 5-201 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-201 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode

BALL BALL NAME PR2_PRU1_PAR_CAP_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
C16 mcasp1_aclkx 1928 0 CFG_MCASP1_ACLKX_IN pr2_pru1_gpi7
D14 mcasp1_axr0 2413 0 CFG_MCASP1_AXR0_IN pr2_pru1_gpi8
B14 mcasp1_axr1 2523 25 CFG_MCASP1_AXR1_IN pr2_pru1_gpi9
B16 mcasp1_axr10 2607 0 CFG_MCASP1_AXR10_IN pr2_pru1_gpi12
B18 mcasp1_axr11 2669 92 CFG_MCASP1_AXR11_IN pr2_pru1_gpi13
A19 mcasp1_axr12 2225 0 CFG_MCASP1_AXR12_IN pr2_pru1_gpi14
E17 mcasp1_axr13 2315 0 CFG_MCASP1_AXR13_IN pr2_pru1_gpi15
E16 mcasp1_axr14 0 0 CFG_MCASP1_AXR14_IN pr2_pru1_gpi16
A18 mcasp1_axr8 2201 0 CFG_MCASP1_AXR8_IN pr2_pru1_gpi10
B17 mcasp1_axr9 2293 278 CFG_MCASP1_AXR9_IN pr2_pru1_gpi11
D23 mcasp4_axr1 1759 0 CFG_MCASP4_AXR1_IN pr2_pru1_gpi0
AC3 mcasp5_aclkx 3732 1810 CFG_MCASP5_ACLKX_IN pr2_pru1_gpi1
AA5 mcasp5_axr0 3776 2255 CFG_MCASP5_AXR0_IN pr2_pru1_gpi3
AC4 mcasp5_axr1 3886 1923 CFG_MCASP5_AXR1_IN pr2_pru1_gpi4
U6 mcasp5_fsx 3800 1449 CFG_MCASP5_FSX_IN pr2_pru1_gpi2
J25 xref_clk0 1375 21 CFG_XREF_CLK0_IN pr2_pru1_gpi5
J24 xref_clk1 1320 0 CFG_XREF_CLK1_IN pr2_pru1_gpi6