SPRS956 Data sheet

SPRS956H March 2016 – November 2019 DRA722 , DRA724 , DRA725 , DRA726

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ABC|760

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprs956h_oa

4.4.5 External Memory Interface (EMIF)

NOTE

For more information, see Memory Subsystem chapter, EMIF Controller section in the device TRM.

NOTE

Dual rank support is not available on this device, but signal names are retained for consistency with the DRA7xx family of devices.

NOTE

ECC is not available on this device, but signal names are retained for consistency with the DRA7xx family of devices.

NOTE

The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Table 4-8, EMIF Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 type of SDRAM memories.

Table 4-8 EMIF Signal Descriptions

SIGNAL NAME	DESCRIPTION	TYPE	BALL
ddr1_csn0	EMIF1 Chip Select 0	O	AH23
ddr1_csn1	EMIF1 Chip Select 1	O	AB16
ddr1_cke	EMIF1 Clock Enable	O	AG22
ddr1_ck	EMIF1 Clock	O	AG24
ddr1_nck	EMIF1 Negative Clock	O	AH24
ddr1_odt0	EMIF1 On-Die Termination for Chip Select 0	O	AE20
ddr1_odt1	EMIF1 On-Die Termination for Chip Select 1	O	AC17
ddr1_casn	EMIF1 Column Address Strobe	O	AC18
ddr1_rasn	EMIF1 Row Address Strobe	O	AF20
ddr1_wen	EMIF1 Write Enable	O	AH21
ddr1_rst	EMIF1 Reset output (DDR3-SDRAM only)	O	AG21
ddr1_ba0	EMIF1 Bank Address	O	AF17
ddr1_ba1	EMIF1 Bank Address	O	AE18
ddr1_ba2	EMIF1 Bank Address	O	AB18
ddr1_a0	EMIF1 Address Bus	O	AD20
ddr1_a1	EMIF1 Address Bus	O	AC19
ddr1_a2	EMIF1 Address Bus	O	AC20
ddr1_a3	EMIF1 Address Bus	O	AB19
ddr1_a4	EMIF1 Address Bus	O	AF21
ddr1_a5	EMIF1 Address Bus	O	AH22
ddr1_a6	EMIF1 Address Bus	O	AG23
ddr1_a7	EMIF1 Address Bus	O	AE21
ddr1_a8	EMIF1 Address Bus	O	AF22
ddr1_a9	EMIF1 Address Bus	O	AE22
ddr1_a10	EMIF1 Address Bus	O	AD21
ddr1_a11	EMIF1 Address Bus	O	AD22
ddr1_a12	EMIF1 Address Bus	O	AC21
ddr1_a13	EMIF1 Address Bus	O	AF18
ddr1_a14	EMIF1 Address Bus	O	AE17
ddr1_a15	EMIF1 Address Bus	O	AD18
ddr1_d0	EMIF1 Data Bus	IO	AF25
ddr1_d1	EMIF1 Data Bus	IO	AF26
ddr1_d2	EMIF1 Data Bus	IO	AG26
ddr1_d3	EMIF1 Data Bus	IO	AH26
ddr1_d4	EMIF1 Data Bus	IO	AF24
ddr1_d5	EMIF1 Data Bus	IO	AE24
ddr1_d6	EMIF1 Data Bus	IO	AF23
ddr1_d7	EMIF1 Data Bus	IO	AE23
ddr1_d8	EMIF1 Data Bus	IO	AC23
ddr1_d9	EMIF1 Data Bus	IO	AF27
ddr1_d10	EMIF1 Data Bus	IO	AG27
ddr1_d11	EMIF1 Data Bus	IO	AF28
ddr1_d12	EMIF1 Data Bus	IO	AE26
ddr1_d13	EMIF1 Data Bus	IO	AC25
ddr1_d14	EMIF1 Data Bus	IO	AC24
ddr1_d15	EMIF1 Data Bus	IO	AD25
ddr1_d16	EMIF1 Data Bus	IO	V20
ddr1_d17	EMIF1 Data Bus	IO	W20
ddr1_d18	EMIF1 Data Bus	IO	AB28
ddr1_d19	EMIF1 Data Bus	IO	AC28
ddr1_d20	EMIF1 Data Bus	IO	AC27
ddr1_d21	EMIF1 Data Bus	IO	Y19
ddr1_d22	EMIF1 Data Bus	IO	AB27
ddr1_d23	EMIF1 Data Bus	IO	Y20
ddr1_d24	EMIF1 Data Bus	IO	AA23
ddr1_d25	EMIF1 Data Bus	IO	Y22
ddr1_d26	EMIF1 Data Bus	IO	Y23
ddr1_d27	EMIF1 Data Bus	IO	AA24
ddr1_d28	EMIF1 Data Bus	IO	Y24
ddr1_d29	EMIF1 Data Bus	IO	AA26
ddr1_d30	EMIF1 Data Bus	IO	AA25
ddr1_d31	EMIF1 Data Bus	IO	AA28
ddr1_ecc_d0	EMIF1 ECC Data Bus	IO	W22
ddr1_ecc_d1	EMIF1 ECC Data Bus	IO	V23
ddr1_ecc_d2	EMIF1 ECC Data Bus	IO	W19
ddr1_ecc_d3	EMIF1 ECC Data Bus	IO	W23
ddr1_ecc_d4	EMIF1 ECC Data Bus	IO	Y25
ddr1_ecc_d5	EMIF1 ECC Data Bus	IO	V24
ddr1_ecc_d6	EMIF1 ECC Data Bus	IO	V25
ddr1_ecc_d7	EMIF1 ECC Data Bus	IO	Y26
ddr1_dqm0	EMIF1 Data Mask	O	AD23
ddr1_dqm1	EMIF1 Data Mask	O	AB23
ddr1_dqm2	EMIF1 Data Mask	O	AC26
ddr1_dqm3	EMIF1 Data Mask	O	AA27
ddr1_dqm_ecc	EMIF1 ECC Data Mask	O	V26
ddr1_dqs0	Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AH25
ddr1_dqsn0	Data strobe 0 invert	IO	AG25
ddr1_dqs1	Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AE27
ddr1_dqsn1	Data strobe 1 invert	IO	AE28
ddr1_dqs2	Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AD27
ddr1_dqsn2	Data strobe 2 invert	IO	AD28
ddr1_dqs3	Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	Y28
ddr1_dqsn3	Data strobe 3 invert	IO	Y27
ddr1_dqs_ecc	EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when writing and input when reading.	IO	V27
ddr1_dqsn_ecc	EMIF1 ECC Complementary Data strobe	IO	V28
ddr1_vref0	Reference Power Supply EMIF1	A	Y18