SPRS989F December   2016  – December 2018 DRA74P , DRA75P

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
    2. 3.2 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  EMIF
      5. 4.3.5  GPMC
      6. 4.3.6  Timers
      7. 4.3.7  I2C
      8. 4.3.8  HDQ1W
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 ATL
      24. 4.3.24 Test Interfaces
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 PRCM
        3. 4.3.25.3 RTC
        4. 4.3.25.4 SDMA
        5. 4.3.25.5 INTC
        6. 4.3.25.6 Observability
        7. 4.3.25.7 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS OSC Buffers DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 BC1833IHHV Buffers DC Electrical Characteristics
      8. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      9. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      10. 5.7.1      HDMIPHY DC Electrical Characteristics
      11. 5.7.2      USBPHY DC Electrical Characteristics
      12. 5.7.3      SATAPHY DC Electrical Characteristics
      13. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RTC Oscillator Input Clock
            1. 5.10.4.1.4.1 RTC Oscillator External Crystal
            2. 5.10.4.1.4.2 RTC Oscillator Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
          3. 5.10.4.4.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  Timers
        9. 5.10.6.9  I2C
          1. Table 5-64 Timing Requirements for I2C Input Timings
          2. Table 5-65 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-66 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        10. 5.10.6.10 HDQ1W
          1. 5.10.6.10.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.10.2 HDQ/1-Wire—1-Wire Mode
        11. 5.10.6.11 UART
          1. Table 5-71 Timing Requirements for UART
          2. Table 5-72 Switching Characteristics Over Recommended Operating Conditions for UART
        12. 5.10.6.12 McSPI
        13. 5.10.6.13 QSPI
        14. 5.10.6.14 McASP
          1. Table 5-79 Timing Requirements for McASP1
          2. Table 5-80 Timing Requirements for McASP2
          3. Table 5-81 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-82 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-83 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-84 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        15. 5.10.6.15 USB
          1. 5.10.6.15.1 USB1 DRD PHY
          2. 5.10.6.15.2 USB2 PHY
          3. 5.10.6.15.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
        16. 5.10.6.16 SATA
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 CAN
          1. 5.10.6.18.1 DCAN
          2. 5.10.6.18.2 MCAN-FD
          3. Table 5-99  Timing Requirements for CANx Receive
          4. Table 5-100 Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-101 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-102 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-103 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-109 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-110 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-111 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-112 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-116 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-117 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-118 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-119 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-Speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-Speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-Speed JC64 DDR, 8-bit data
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 ATL
          1. 5.10.6.23.1 ATL Electrical Data/Timing
            1. Table 5-175 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
        24. 5.10.6.24 System and Miscellaneous Interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-176 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-177 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-178 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-179 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  ISS
    6. 6.6  IVA
    7. 6.7  EVE
    8. 6.8  IPU
    9. 6.9  VPE
    10. 6.10 GPU
    11. 6.11 ATL Overview
    12. 6.12 Memory Subsystem
      1. 6.12.1 EMIF
      2. 6.12.2 GPMC
      3. 6.12.3 ELM
      4. 6.12.4 OCMC
    13. 6.13 Interprocessor Communication
      1. 6.13.1 Mailbox
      2. 6.13.2 Spinlock
    14. 6.14 Interrupt Controller
    15. 6.15 EDMA
    16. 6.16 Peripherals
      1. 6.16.1  VIP
      2. 6.16.2  DSS
      3. 6.16.3  Timers
      4. 6.16.4  I2C
      5. 6.16.5  HDQ1W
      6. 6.16.6  UART
        1. 6.16.6.1 UART Features
        2. 6.16.6.2 IrDA Features
        3. 6.16.6.3 CIR Features
      7. 6.16.7  McSPI
      8. 6.16.8  QSPI
      9. 6.16.9  McASP
      10. 6.16.10 USB
      11. 6.16.11 SATA
      12. 6.16.12 PCIe
      13. 6.16.13 CAN
      14. 6.16.14 GMAC_SW
      15. 6.16.15 MLB
      16. 6.16.16 eMMC/SD/SDIO
      17. 6.16.17 GPIO
      18. 6.16.18 ePWM
      19. 6.16.19 eCAP
      20. 6.16.20 eQEP
    17. 6.17 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_mpu Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 JTAG Interface
            11. 7.5.2.2.2.11 Power Regulators
        3. 7.5.2.3 Electrostatic Discharge (ESD)
          1. 7.5.2.3.1 IEC ESD Stressing Test
            1. 7.5.2.3.1.1 Test Mode
            2. 7.5.2.3.1.2 Air Discharge Mode
            3. 7.5.2.3.1.3 Test Type
          2. 7.5.2.3.2 TI Component Level IEC ESD Test
          3. 7.5.2.3.3 Construction of a Custom USB Connector
          4. 7.5.2.3.4 ESD Protection System Design Consideration
        4. 7.5.2.4 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 SATA Board Design and Layout Guidelines
        1. 7.5.5.1 SATA Interface Schematic
        2. 7.5.5.2 Compatible SATA Components and Modes
        3. 7.5.5.3 PCB Stackup Specifications
        4. 7.5.5.4 Routing Specifications
      6. 7.5.6 PCIe Board Design and Layout Guidelines
        1. 7.5.6.1 PCIe Connections and Interface Compliance
          1. 7.5.6.1.1 Coupling Capacitors
          2. 7.5.6.1.2 Polarity Inversion
        2. 7.5.6.2 Non-standard PCIe connections
          1. 7.5.6.2.1 PCB Stackup Specifications
          2. 7.5.6.2.2 Routing Specifications
            1. 7.5.6.2.2.1 Impedance
            2. 7.5.6.2.2.2 Differential Coupling
            3. 7.5.6.2.2.3 Pair Length Matching
        3. 7.5.6.3 LJCB_REFN/P Connections
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 32-kHz Oscillator Routing
      2. 7.6.2 Oscillator Ground Connection
    7. 7.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High-Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 7.7.3 DDR3 Board Design and Layout Guidelines
        1. 7.7.3.1  Board Designs
        2. 7.7.3.2  DDR3 EMIF
        3. 7.7.3.3  DDR3 Device Combinations
        4. 7.7.3.4  DDR3 Interface Schematic
          1. 7.7.3.4.1 32-Bit DDR3 Interface
          2. 7.7.3.4.2 16-Bit DDR3 Interface
        5. 7.7.3.5  Compatible JEDEC DDR3 Devices
        6. 7.7.3.6  PCB Stackup
        7. 7.7.3.7  Placement
        8. 7.7.3.8  DDR3 Keepout Region
        9. 7.7.3.9  Bulk Bypass Capacitors
        10. 7.7.3.10 High-Speed Bypass Capacitors
          1. 7.7.3.10.1 Return Current Bypass Capacitors
        11. 7.7.3.11 Net Classes
        12. 7.7.3.12 DDR3 Signal Termination
        13. 7.7.3.13 VREF_DDR Routing
        14. 7.7.3.14 VTT
        15. 7.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.3.15.1 Four DDR3 Devices
            1. 7.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.3.15.2 Two DDR3 Devices
            1. 7.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.3.15.3 One DDR3 Device
            1. 7.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.3.16 Data Topologies and Routing Definition
          1. 7.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.3.17 Routing Specification
          1. 7.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.3.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1  Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2  Tools and Software
    3. 8.3  Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4  Receiving Notification of Documentation Updates
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABZ|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10.6.3 VIP

The Device includes 2 Video Input Ports (VIP).

Table 5-34, Figure 5-25 and Figure 5-26 present timings and switching characteristics of the VIPs.

CAUTION

The IO timings provided in this section are applicable for all combinations of signals for vin1. However, the timings are only valid for vin2, vin3, and vin4 if signals within a single IOSET are used. The IOSETs are defined in the Table 5-35, Table 5-36 and Table 5-37.

Table 5-34 Timing Requirements for VIP(1)(3)(4)(5)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
V1 tc(CLK) Cycle time, vinx_clki (3)(5) 6.06 ns
V2 tw(CLKH) Pulse duration, vinx_clki high (3)(5) 0.45P (2) ns
V3 tw(CLKL) Pulse duration, vinx_clki low (3)(5) 0.45P (2) ns
V4 tsu(CTL/DATA-CLK) Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3)(4)(5) vin1x, vin2x 2.93 ns
vin3x, vin4x 3.11 ns
V5 th(CLK-CTL/DATA) Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid from vinx_clki transition (3)(4)(5) -0.05 ns
  1. For maximum frequency of 165 MHZ.
  2. P = vinx_clki period.
  3. x in vinx = 1a, 1b, 2a, 2b, 3a, 3b, 4a, 4b.
  4. n in dn = 0 to 7 when x = 1b, 2b, 3b and 4b;
    n = 0 to 23 when x = 1a, 2a, 3a and 4a;
  5. i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
DRA75P DRA74P SPRS8xx_VIP_01.gifFigure 5-25 Video Input Ports clock signal
DRA75P DRA74P SPRS8xx_VIP_02.gifFigure 5-26 Video Input Ports timings

In Table 5-35, Table 5-36 and Table 5-37 are presented the specific groupings of signals (IOSET) for use with vin2, vin3, and vin4.

Table 5-35 VIN2 IOSETs

Signals IOSET1 IOSET2 IOSET3
BALL MUX BALL MUX BALL MUX
vin2a
vin2a_d0 F2 0 F2 0 U4 4
vin2a_d1 F3 0 F3 0 V2 4
vin2a_d2 D1 0 D1 0 Y1 4
vin2a_d3 E2 0 E2 0 W9 4
vin2a_d4 D2 0 D2 0 V9 4
vin2a_d5 F4 0 F4 0 U5 4
vin2a_d6 C1 0 C1 0 V5 4
vin2a_d7 E4 0 E4 0 V4 4
vin2a_d8 F5 0 F5 0 V3 4
vin2a_d9 E6 0 E6 0 Y2 4
vin2a_d10 D3 0 D3 0 U6 4
vin2a_d11 F6 0 F6 0 U3 4
vin2a_d12 D5 0 D5 0 - -
vin2a_d13 C2 0 C2 0 - -
vin2a_d14 C3 0 C3 0 - -
vin2a_d15 C4 0 C4 0 - -
vin2a_d16 B2 0 B2 0 - -
vin2a_d17 D6 0 D6 0 - -
vin2a_d18 C5 0 C5 0 - -
vin2a_d19 A3 0 A3 0 - -
vin2a_d20 B3 0 B3 0 - -
vin2a_d21 B4 0 B4 0 - -
vin2a_d22 B5 0 B5 0 - -
vin2a_d23 A4 0 A4 0 - -
vin2a_hsync0 G1 0 G1 0 U7 4
vin2a_vsync0 G6 0 G6 0 V6 4
vin2a_de0 G2 0 - - V7 4
vin2a_fld0 H7 0 G2 1 W2 4
vin2a_clk0 E1 0 E1 0 V1 4
vin2b
vin2b_clk1 H7 2 H7 2 AB5 4
vin2b_de1 - - G2 3 AB8 4
vin2b_fld1 G2 2 - - - -
vin2b_d0 A4 2 A4 2 AD6 4
vin2b_d1 B5 2 B5 2 AC8 4
vin2b_d2 B4 2 B4 2 AC3 4
vin2b_d3 B3 2 B3 2 AC9 4
vin2b_d4 A3 2 A3 2 AC6 4
vin2b_d5 C5 2 C5 2 AC7 4
vin2b_d6 D6 2 D6 2 AC4 4
vin2b_d7 B2 2 B2 2 AD4 4
vin2b_hsync1 G1 3 G1 3 AC5 4
vin2b_vsync1 G6 3 G6 3 AB4 4

Table 5-36 VIN3 IOSETs

Signals IOSET1 IOSET2 IOSET3 IOSET4
BALL MUX BALL MUX BALL MUX BALL MUX
vin3a
vin3a_d0 M6 2 AF1 6 AF1 6 B7 4
vin3a_d1 M2 2 AE3 6 AE3 6 B8 4
vin3a_d2 L5 2 AE5 6 AE5 6 A7 4
vin3a_d3 M1 2 AE1 6 AE1 6 A8 4
vin3a_d4 L6 2 AE2 6 AE2 6 C9 4
vin3a_d5 L4 2 AE6 6 AE6 6 A9 4
vin3a_d6 L3 2 AD2 6 AD2 6 B9 4
vin3a_d7 L2 2 AD3 6 AD3 6 A10 4
vin3a_d8 L1 2 B2 6 B2 6 E8 4
vin3a_d9 K2 2 D6 6 D6 6 D9 4
vin3a_d10 J1 2 C5 6 C5 6 D7 4
vin3a_d11 J2 2 A3 6 A3 6 D8 4
vin3a_d12 H1 2 B3 6 - - A5 4
vin3a_d13 J3 2 B4 6 - - C6 4
vin3a_d14 H2 2 B5 6 - - C8 4
vin3a_d15 H3 2 A4 6 - - C7 4
vin3a_d16 R6 2 - - - - F11 4
vin3a_d17 T9 2 - - - - G10 4
vin3a_d18 T6 2 - - - - F10 4
vin3a_d19 T7 2 - - - - G11 4
vin3a_d20 P6 2 - - - - E9 4
vin3a_d21 R9 2 - - - - F9 4
vin3a_d22 R5 2 - - - - F8 4
vin3a_d23 P5 2 - - - - E7 4
vin3a_hsync0 N7 2 N7 2 B5 5 C11 4
vin3a_vsync0 R4 2 R4 2 A4 5 E11 4
vin3a_de0 N9 2 N9 2 B3 5 B10 4
vin3a_fld0 P9 2 P9 2 B4 5 D11 4
vin3a_clk0 P1 2 AH7 6 AH7 6 B11 4
vin3b
vin3b_clk1 P7 6 M4 4 - - - -
vin3b_de1 N6 6 N6 6 - - - -
vin3b_fld1 M4 6 - - - - - -
vin3b_d0 K7 6 K7 6 - - - -
vin3b_d1 M7 6 M7 6 - - - -
vin3b_d2 J5 6 J5 6 - - - -
vin3b_d3 K6 6 K6 6 - - - -
vin3b_d4 J7 6 J7 6 - - - -
vin3b_d5 J4 6 J4 6 - - - -
vin3b_d6 J6 6 J6 6 - - - -
vin3b_d7 H4 6 H4 6 - - - -
vin3b_hsync1 H5 6 H5 6 - - - -
vin3b_vsync1 H6 6 H6 6 - - - -

Table 5-37 VIN4 IOSETs

Signals IOSET1 IOSET2 IOSET3
BALL MUX BALL MUX BALL MUX
vin4a
vin4a_d0 R6 4 B7 3 B14 8
vin4a_d1 T9 4 B8 3 J14 8
vin4a_d2 T6 4 A7 3 G13 8
vin4a_d3 T7 4 A8 3 J11 8
vin4a_d4 P6 4 C9 3 E12 8
vin4a_d5 R9 4 A9 3 F13 8
vin4a_d6 R5 4 B9 3 C12 8
vin4a_d7 P5 4 A10 3 D12 8
vin4a_d8 U2 4 E8 3 E15 8
vin4a_d9 U1 4 D9 3 A20 8
vin4a_d10 P3 4 D7 3 B15 8
vin4a_d11 R2 4 D8 3 A15 8
vin4a_d12 K7 4 A5 3 D15 8
vin4a_d13 M7 4 C6 3 B16 8
vin4a_d14 J5 4 C8 3 B17 8
vin4a_d15 K6 4 C7 3 A17 8
vin4a_d16 - - F11 3 C18 8
vin4a_d17 - - G10 3 A21 8
vin4a_d18 - - F10 3 G16 8
vin4a_d19 - - G11 3 D17 8
vin4a_d20 - - E9 3 AA3 8
vin4a_d21 - - F9 3 AB9 8
vin4a_d22 - - F8 3 AB3 8
vin4a_d23 - - E7 3 AA4 8
vin4a_hsync0 R3/P7 4 / 4 C11 3 E21 8
vin4a_vsync0 T2/N1 4 / 4 E11 3 F20 8
vin4a_de0 H6/P7 4 / 5 B10 3 C23 8
vin4a_fld0 P9/J7 4 / 4 D11 3 F21 8
vin4a_clk0 P4 4 B11 3 B26 8
vin4b
vin4b_clk1 N9 6 V1 5 - -
vin4b_de1 P9 6 V7 5 - -
vin4b_fld1 P4 6 W2 5 - -
vin4b_d0 R6 6 U4 5 - -
vin4b_d1 T9 6 V2 5 - -
vin4b_d2 T6 6 Y1 5 - -
vin4b_d3 T7 6 W9 5 - -
vin4b_d4 P6 6 V9 5 - -
vin4b_d5 R9 6 U5 5 - -
vin4b_d6 R5 6 V5 5 - -
vin4b_d7 P5 6 V4 5 - -
vin4b_hsync1 N7 6 U7 5 - -
vin4b_vsync1 R4 6 V6 5 - -


NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to guarantee some IO timings for VIP1. See Table 5-33Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-38Manual Functions Mapping for VIP1 for a definition of the Manual modes.

Table 5-38 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-38 Manual Functions Mapping for VIP1

BALL BALL NAME VIP1_MANUAL1 VIP1_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 0 1 2 3 4
U3 RMII_MHZ_50_CLK 1973 184 2257 0 CFG_RMII_MHZ_50_CLK_IN - - - - vin2a_d11
N6 gpmc_ben0 2133 486 2582 77 CFG_GPMC_BEN0_IN - - - vin1b_hsync1 -
M4 gpmc_ben1 2034 577 2545 109 CFG_GPMC_BEN1_IN - - - vin1b_de1 -
U4 mdio_d 1897 35 1999 0 CFG_MDIO_D_IN - - - - vin2a_d0
V1 mdio_mclk 0 0 0 0 CFG_MDIO_MCLK_IN - - - - vin2a_clk0
U5 rgmii0_rxc 1945 97 2072 0 CFG_RGMII0_RXC_IN - - - - vin2a_d5
V5 rgmii0_rxctl 1939 440 2326 93 CFG_RGMII0_RXCTL_IN - - - - vin2a_d6
W2 rgmii0_rxd0 1990 141 2147 0 CFG_RGMII0_RXD0_IN - - - - vin2a_fld0
Y2 rgmii0_rxd1 1928 527 2298 246 CFG_RGMII0_RXD1_IN - - - - vin2a_d9
V3 rgmii0_rxd2 1901 425 2280 134 CFG_RGMII0_RXD2_IN - - - - vin2a_d8
V4 rgmii0_rxd3 1972 637 2331 362 CFG_RGMII0_RXD3_IN - - - - vin2a_d7
W9 rgmii0_txc 1933 382 2347 28 CFG_RGMII0_TXC_IN - - - - vin2a_d3
V9 rgmii0_txctl 2019 479 2372 217 CFG_RGMII0_TXCTL_IN - - - - vin2a_d4
U6 rgmii0_txd0 1934 203 2205 0 CFG_RGMII0_TXD0_IN - - - - vin2a_d10
V6 rgmii0_txd1 2015 604 2360 362 CFG_RGMII0_TXD1_IN - - - - vin2a_vsync0
U7 rgmii0_txd2 1839 496 2249 158 CFG_RGMII0_TXD2_IN - - - - vin2a_hsync0
V7 rgmii0_txd3 2087 423 2426 108 CFG_RGMII0_TXD3_IN - - - - vin2a_de0
V2 uart3_rxd 1578 0 1530 0 CFG_UART3_RXD_IN - - - - vin2a_d1
Y1 uart3_txd 1869 99 1967 0 CFG_UART3_TXD_IN - - - - vin2a_d2
AG8 vin1a_clk0 0 0 0 0 CFG_VIN1A_CLK0_IN vin1a_clk0 - - - -
AE8 vin1a_d0 2051 708 2439 275 CFG_VIN1A_D0_IN vin1a_d0 - - - -
AD8 vin1a_d1 1931 812 2337 447 CFG_VIN1A_D1_IN vin1a_d1 - - - -
AG3 vin1a_d10 2049 804 2420 448 CFG_VIN1A_D10_IN vin1a_d10 vin1b_d5 - - -
AG5 vin1a_d11 1921 766 2331 438 CFG_VIN1A_D11_IN vin1a_d11 vin1b_d4 - - -
AF2 vin1a_d12 2078 1220 2397 915 CFG_VIN1A_D12_IN vin1a_d12 vin1b_d3 - - -
AF6 vin1a_d13 1986 1138 2366 788 CFG_VIN1A_D13_IN vin1a_d13 vin1b_d2 - - -
AF3 vin1a_d14 2077 1242 2403 947 CFG_VIN1A_D14_IN vin1a_d14 vin1b_d1 - - -
AF4 vin1a_d15 2070 1581 2337 1407 CFG_VIN1A_D15_IN vin1a_d15 vin1b_d0 - - -
AF1 vin1a_d16 2008 1432 2321 1202 CFG_VIN1A_D16_IN vin1a_d16 vin1b_d7 - - -
AE3 vin1a_d17 2077 1571 2370 1351 CFG_VIN1A_D17_IN vin1a_d17 vin1b_d6 - - -
AE5 vin1a_d18 2075 1527 2357 1292 CFG_VIN1A_D18_IN vin1a_d18 vin1b_d5 - - -
AE1 vin1a_d19 2055 1636 2358 1422 CFG_VIN1A_D19_IN vin1a_d19 vin1b_d4 - - -
AG7 vin1a_d2 1871 1037 2301 620 CFG_VIN1A_D2_IN vin1a_d2 - - - -
AE2 vin1a_d20 2046 1452 2351 1163 CFG_VIN1A_D20_IN vin1a_d20 vin1b_d3 - - -
AE6 vin1a_d21 2135 1292 2405 1024 CFG_VIN1A_D21_IN vin1a_d21 vin1b_d2 - - -
AD2 vin1a_d22 2034 1430 2348 1206 CFG_VIN1A_D22_IN vin1a_d22 vin1b_d1 - - -
AD3 vin1a_d23 2191 813 2502 447 CFG_VIN1A_D23_IN vin1a_d23 vin1b_d0 - - -
AH6 vin1a_d3 1938 984 2299 658 CFG_VIN1A_D3_IN vin1a_d3 - - - -
AH3 vin1a_d4 2034 597 2424 178 CFG_VIN1A_D4_IN vin1a_d4 - - - -
AH5 vin1a_d5 1961 927 2359 554 CFG_VIN1A_D5_IN vin1a_d5 - - - -
AG6 vin1a_d6 1909 930 2323 549 CFG_VIN1A_D6_IN vin1a_d6 - - - -
AH4 vin1a_d7 1999 901 2383 557 CFG_VIN1A_D7_IN vin1a_d7 - - - -
AG4 vin1a_d8 2040 856 2426 448 CFG_VIN1A_D8_IN vin1a_d8 vin1b_d7 - - -
AG2 vin1a_d9 2133 799 2472 388 CFG_VIN1A_D9_IN vin1a_d9 vin1b_d6 - - -
AD9 vin1a_de0 1842 861 2258 352 CFG_VIN1A_DE0_IN vin1a_de0 vin1b_hsync1 - - -
AF9 vin1a_fld0 1968 1029 2347 622 CFG_VIN1A_FLD0_IN vin1a_fld0 vin1b_vsync1 - - -
AE9 vin1a_hsync0 1871 1264 2257 881 CFG_VIN1A_HSYNC0_IN vin1a_hsync0 vin1b_fld1 - - -
AF8 vin1a_vsync0 1798 1000 2243 649 CFG_VIN1A_VSYNC0_IN vin1a_vsync0 vin1b_de1 - - -
AH7 vin1b_clk1 160 0 227 0 CFG_VIN1B_CLK1_IN vin1b_clk1 - - - -
E1 vin2a_clk0 0 0 0 0 CFG_VIN2A_CLK0_IN vin2a_clk0 - - - -
F2 vin2a_d0 1920 227 2180 0 CFG_VIN2A_D0_IN vin2a_d0 - - - -
F3 vin2a_d1 1957 476 2326 309 CFG_VIN2A_D1_IN vin2a_d1 - - - -
D3 vin2a_d10 1865 337 2297 110 CFG_VIN2A_D10_IN vin2a_d10 - - - -
F6 vin2a_d11 1753 19 1938 0 CFG_VIN2A_D11_IN vin2a_d11 - - - -
D5 vin2a_d12 1654 487 2135 182 CFG_VIN2A_D12_IN vin2a_d12 - - - -
C2 vin2a_d13 1927 132 2134 0 CFG_VIN2A_D13_IN vin2a_d13 - - - -
C3 vin2a_d14 1715 0 1753 0 CFG_VIN2A_D14_IN vin2a_d14 - - - -
C4 vin2a_d15 1745 381 2222 63 CFG_VIN2A_D15_IN vin2a_d15 - - - -
B2 vin2a_d16 1670 319 2137 58 CFG_VIN2A_D16_IN vin2a_d16 - vin2b_d7 - -
D6 vin2a_d17 1709 409 2192 79 CFG_VIN2A_D17_IN vin2a_d17 - vin2b_d6 - -
C5 vin2a_d18 2033 334 2378 21 CFG_VIN2A_D18_IN vin2a_d18 - vin2b_d5 - -
A3 vin2a_d19 1957 193 2207 0 CFG_VIN2A_D19_IN vin2a_d19 - vin2b_d4 - -
D1 vin2a_d2 1912 5 2057 0 CFG_VIN2A_D2_IN vin2a_d2 - - - -
B3 vin2a_d20 1938 619 2325 388 CFG_VIN2A_D20_IN vin2a_d20 - vin2b_d3 - -
B4 vin2a_d21 1899 546 2320 221 CFG_VIN2A_D21_IN vin2a_d21 - vin2b_d2 - -
B5 vin2a_d22 1800 272 2219 30 CFG_VIN2A_D22_IN vin2a_d22 - vin2b_d1 - -
A4 vin2a_d23 1807 476 2225 200 CFG_VIN2A_D23_IN vin2a_d23 - vin2b_d0 - -
E2 vin2a_d3 2095 421 2440 257 CFG_VIN2A_D3_IN vin2a_d3 - - - -
D2 vin2a_d4 2008 0 2142 0 CFG_VIN2A_D4_IN vin2a_d4 - - - -
F4 vin2a_d5 2137 406 2455 252 CFG_VIN2A_D5_IN vin2a_d5 - - - -
C1 vin2a_d6 1717 0 1883 0 CFG_VIN2A_D6_IN vin2a_d6 - - - -
E4 vin2a_d7 1850 171 2229 0 CFG_VIN2A_D7_IN vin2a_d7 - - - -
F5 vin2a_d8 1841 340 2250 151 CFG_VIN2A_D8_IN vin2a_d8 - - - -
E6 vin2a_d9 1836 289 2279 27 CFG_VIN2A_D9_IN vin2a_d9 - - - -
G2 vin2a_de0 1772 316 2202 0 CFG_VIN2A_DE0_IN vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 -
H7 vin2a_fld0 2117 507 2453 357 CFG_VIN2A_FLD0_IN vin2a_fld0 - vin2b_clk1 - -
G1 vin2a_hsync0 1969 231 2233 0 CFG_VIN2A_HSYNC0_IN vin2a_hsync0 - - vin2b_hsync1 -
G6 vin2a_vsync0 1793 110 1936 0 CFG_VIN2A_VSYNC0_IN vin2a_vsync0 - - vin2b_vsync1 -

Manual IO Timings Modes must be used to guarantee some IO timings for VIP1. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-39, Manual Functions Mapping for VIP1 2B for a definition of the Manual modes.

Table 5-39 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-39 Manual Functions Mapping for VIP1 2B

BALL BALL NAME VIP1_2B_MANUAL1 VIP1_2B_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 2 3 4
AC5 gpio6_10 2207 0 2288 0 CFG_GPIO6_10_IN - - vin2b_hsync1
AB4 gpio6_11 2183 225 2486 77 CFG_GPIO6_11_IN - - vin2b_vsync1
AD4 mmc3_clk 2262 114 2452 0 CFG_MMC3_CLK_IN - - vin2b_d7
AC4 mmc3_cmd 2228 108 2425 0 CFG_MMC3_CMD_IN - - vin2b_d6
AC7 mmc3_dat0 2137 170 2463 0 CFG_MMC3_DAT0_IN - - vin2b_d5
AC6 mmc3_dat1 2116 154 2393 0 CFG_MMC3_DAT1_IN - - vin2b_d4
AC9 mmc3_dat2 1891 0 1945 0 CFG_MMC3_DAT2_IN - - vin2b_d3
AC3 mmc3_dat3 2202 197 2516 22 CFG_MMC3_DAT3_IN - - vin2b_d2
AC8 mmc3_dat4 1966 0 1991 0 CFG_MMC3_DAT4_IN - - vin2b_d1
AD6 mmc3_dat5 2163 15 2361 0 CFG_MMC3_DAT5_IN - - vin2b_d0
AB8 mmc3_dat6 2162 51 2319 0 CFG_MMC3_DAT6_IN - - vin2b_de1
AB5 mmc3_dat7 0 0 0 0 CFG_MMC3_DAT7_IN - - vin2b_clk1
B2 vin2a_d16 1175 0 1413 0 CFG_VIN2A_D16_IN vin2b_d7 - -
D6 vin2a_d17 1323 0 1522 0 CFG_VIN2A_D17_IN vin2b_d6 - -
C5 vin2a_d18 1513 0 1580 0 CFG_VIN2A_D18_IN vin2b_d5 - -
A3 vin2a_d19 1278 0 1396 0 CFG_VIN2A_D19_IN vin2b_d4 - -
B3 vin2a_d20 1676 0 1895 0 CFG_VIN2A_D20_IN vin2b_d3 - -
B4 vin2a_d21 1610 0 1774 0 CFG_VIN2A_D21_IN vin2b_d2 - -
B5 vin2a_d22 1250 0 1497 0 CFG_VIN2A_D22_IN vin2b_d1 - -
A4 vin2a_d23 1434 0 1643 0 CFG_VIN2A_D23_IN vin2b_d0 - -
G2 vin2a_de0 1539 147 1793 0 CFG_VIN2A_DE0_IN vin2b_fld1 vin2b_de1 -
H7 vin2a_fld0 0 0 0 0 CFG_VIN2A_FLD0_IN vin2b_clk1 - -
G1 vin2a_hsync0 1475 0 1542 0 CFG_VIN2A_HSYNC0_IN - vin2b_hsync1 -
G6 vin2a_vsync0 1163 0 1218 0 CFG_VIN2A_VSYNC0_IN - vin2b_vsync1 -
  1. The CFG_MMC3_CLK_IN register should remain at its Default value, which is programmed automatically by hardware during the recalibration process.

Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-40, Manual Functions Mapping for VIP2 for a definition of the Manual modes.

Table 5-40 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-40 Manual Functions Mapping for VIP2

BALL BALL NAME VIP2_MANUAL 1 VIP2_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 2 3 4 5 6
R6 gpmc_a0 2558 565 2920 260 CFG_GPMC_A0_IN vin3a_d16 - vin4a_d0 - -
T9 gpmc_a1 2421 648 2782 349 CFG_GPMC_A1_IN vin3a_d17 - vin4a_d1 - -
N9 gpmc_a10 2378 477 2765 0 CFG_GPMC_A10_IN vin3a_de0 - - - -
P9 gpmc_a11 2409 579 2783 295 CFG_GPMC_A11_IN vin3a_fld0 - vin4a_fld0 - -
K7 gpmc_a19 1887 0 1735 0 CFG_GPMC_A19_IN - - vin4a_d12 - vin3b_d0
T6 gpmc_a2 2624 893 2882 682 CFG_GPMC_A2_IN vin3a_d18 - vin4a_d2 - -
M7 gpmc_a20 1670 0 1508 0 CFG_GPMC_A20_IN - - vin4a_d13 - vin3b_d1
J5 gpmc_a21 1925 0 1763 0 CFG_GPMC_A21_IN - - vin4a_d14 - vin3b_d2
K6 gpmc_a22 1777 0 1631 0 CFG_GPMC_A22_IN - - vin4a_d15 - vin3b_d3
J7 gpmc_a23 1716 0 1717 0 CFG_GPMC_A23_IN - - vin4a_fld0 - vin3b_d4
J4 gpmc_a24 1758 111 1756 0 CFG_GPMC_A24_IN - - - - vin3b_d5
J6 gpmc_a25 1805 0 1667 0 CFG_GPMC_A25_IN - - - - vin3b_d6
H4 gpmc_a26 1800 54 1699 0 CFG_GPMC_A26_IN - - - - vin3b_d7
H5 gpmc_a27 1661 0 1540 0 CFG_GPMC_A27_IN - - - - vin3b_hsync1
T7 gpmc_a3 2589 902 2855 715 CFG_GPMC_A3_IN vin3a_d19 - vin4a_d3 - -
P6 gpmc_a4 2616 808 2874 597 CFG_GPMC_A4_IN vin3a_d20 - vin4a_d4 - -
R9 gpmc_a5 2514 733 2842 491 CFG_GPMC_A5_IN vin3a_d21 - vin4a_d5 - -
R5 gpmc_a6 2511 417 2837 146 CFG_GPMC_A6_IN vin3a_d22 - vin4a_d6 - -
P5 gpmc_a7 2752 618 3035 325 CFG_GPMC_A7_IN vin3a_d23 - vin4a_d7 - -
N7 gpmc_a8 2457 603 2812 203 CFG_GPMC_A8_IN vin3a_hsync0 - - - -
R4 gpmc_a9 2536 749 2857 409 CFG_GPMC_A9_IN vin3a_vsync0 - - - -
M6 gpmc_ad0 2139 232 2444 0 CFG_GPMC_AD0_IN vin3a_d0 - - - -
M2 gpmc_ad1 2429 212 2711 0 CFG_GPMC_AD1_IN vin3a_d1 - - - -
J1 gpmc_ad10 2294 337 2703 16 CFG_GPMC_AD10_IN vin3a_d10 - - - -
J2 gpmc_ad11 2184 327 2600 0 CFG_GPMC_AD11_IN vin3a_d11 - - - -
H1 gpmc_ad12 2222 182 2471 0 CFG_GPMC_AD12_IN vin3a_d12 - - - -
J3 gpmc_ad13 2179 152 2421 0 CFG_GPMC_AD13_IN vin3a_d13 - - - -
H2 gpmc_ad14 2166 16 2263 0 CFG_GPMC_AD14_IN vin3a_d14 - - - -
H3 gpmc_ad15 2191 254 2535 0 CFG_GPMC_AD15_IN vin3a_d15 - - - -
L5 gpmc_ad2 2412 314 2776 41 CFG_GPMC_AD2_IN vin3a_d2 - - - -
M1 gpmc_ad3 2249 227 2503 0 CFG_GPMC_AD3_IN vin3a_d3 - - - -
L6 gpmc_ad4 2317 256 2613 0 CFG_GPMC_AD4_IN vin3a_d4 - - - -
L4 gpmc_ad5 2254 108 2441 0 CFG_GPMC_AD5_IN vin3a_d5 - - - -
L3 gpmc_ad6 2164 279 2533 0 CFG_GPMC_AD6_IN vin3a_d6 - - - -
L2 gpmc_ad7 2278 230 2597 0 CFG_GPMC_AD7_IN vin3a_d7 - - - -
L1 gpmc_ad8 2246 449 2701 84 CFG_GPMC_AD8_IN vin3a_d8 - - - -
K2 gpmc_ad9 2222 298 2607 0 CFG_GPMC_AD9_IN vin3a_d9 - - - -
N6 gpmc_ben0 1767 0 1686 0 CFG_GPMC_BEN0_IN - - - - vin3b_de1
M4 gpmc_ben1 1838 0 1766 0 CFG_GPMC_BEN1_IN - - vin3b_clk1 - vin3b_fld1
P7 gpmc_clk 0 0 0 0 CFG_GPMC_CLK_IN - - vin4a_hsync0 vin4a_de0 vin3b_clk1
H6 gpmc_cs1 1611 0 1450 0 CFG_GPMC_CS1_IN - - vin4a_de0 - vin3b_vsync1
P1 gpmc_cs3 0 0 0 0 CFG_GPMC_CS3_IN vin3a_clk0 - - - -
AF1 vin1a_d16 2152 1311 2633 790 CFG_VIN1A_D16_IN - - - - vin3a_d0
AE3 vin1a_d17 2211 1381 2690 849 CFG_VIN1A_D17_IN - - - - vin3a_d1
AE5 vin1a_d18 2220 1393 2669 879 CFG_VIN1A_D18_IN - - - - vin3a_d2
AE1 vin1a_d19 2186 1418 2680 870 CFG_VIN1A_D19_IN - - - - vin3a_d3
AE2 vin1a_d20 2183 1292 2666 707 CFG_VIN1A_D20_IN - - - - vin3a_d4
AE6 vin1a_d21 2280 1155 2721 601 CFG_VIN1A_D21_IN - - - - vin3a_d5
AD2 vin1a_d22 2144 1098 2664 517 CFG_VIN1A_D22_IN - - - - vin3a_d6
AD3 vin1a_d23 2355 643 2816 0 CFG_VIN1A_D23_IN - - - - vin3a_d7
AH7 vin1b_clk1 0 0 0 0 CFG_VIN1B_CLK1_IN - - - - vin3a_clk0
B2 vin2a_d16 1624 239 1772 0 CFG_VIN2A_D16_IN - - - - vin3a_d8
D6 vin2a_d17 1541 406 1838 0 CFG_VIN2A_D17_IN - - - - vin3a_d9
C5 vin2a_d18 1942 313 2047 0 CFG_VIN2A_D18_IN - - - - vin3a_d10
A3 vin2a_d19 1851 0 1667 0 CFG_VIN2A_D19_IN - - - - vin3a_d11
B3 vin2a_d20 1837 430 2187 0 CFG_VIN2A_D20_IN - - - vin3a_de0 vin3a_d12
B4 vin2a_d21 1805 400 2042 0 CFG_VIN2A_D21_IN - - - vin3a_fld0 vin3a_d13
B5 vin2a_d22 1667 213 1786 0 CFG_VIN2A_D22_IN - - - vin3a_hsync0 vin3a_d14
A4 vin2a_d23 1700 408 2010 0 CFG_VIN2A_D23_IN - - - vin3a_vsync0 vin3a_d15
D11 vout1_clk 2405 379 2780 257 CFG_VOUT1_CLK_IN - vin4a_fld0 vin3a_fld0 - -
F11 vout1_d0 2475 548 2806 469 CFG_VOUT1_D0_IN - vin4a_d16 vin3a_d16 - -
G10 vout1_d1 2382 554 2771 418 CFG_VOUT1_D1_IN - vin4a_d17 vin3a_d17 - -
D7 vout1_d10 2379 420 2784 267 CFG_VOUT1_D10_IN - vin4a_d10 vin3a_d10 - -
D8 vout1_d11 2472 453 2810 367 CFG_VOUT1_D11_IN - vin4a_d11 vin3a_d11 - -
A5 vout1_d12 2370 401 2777 247 CFG_VOUT1_D12_IN - vin4a_d12 vin3a_d12 - -
C6 vout1_d13 2437 375 2819 229 CFG_VOUT1_D13_IN - vin4a_d13 vin3a_d13 - -
C8 vout1_d14 2466 433 2785 342 CFG_VOUT1_D14_IN - vin4a_d14 vin3a_d14 - -
C7 vout1_d15 2465 383 2846 255 CFG_VOUT1_D15_IN - vin4a_d15 vin3a_d15 - -
B7 vout1_d16 2411 236 2733 167 CFG_VOUT1_D16_IN - vin4a_d0 vin3a_d0 - -
B8 vout1_d17 2541 435 2840 379 CFG_VOUT1_D17_IN - vin4a_d1 vin3a_d1 - -
A7 vout1_d18 2451 244 2761 186 CFG_VOUT1_D18_IN - vin4a_d2 vin3a_d2 - -
A8 vout1_d19 2366 0 2564 0 CFG_VOUT1_D19_IN - vin4a_d3 vin3a_d3 - -
F10 vout1_d2 2373 639 2740 526 CFG_VOUT1_D2_IN - vin4a_d18 vin3a_d18 - -
C9 vout1_d20 2381 578 2758 454 CFG_VOUT1_D20_IN - vin4a_d4 vin3a_d4 - -
A9 vout1_d21 2349 104 2706 0 CFG_VOUT1_D21_IN - vin4a_d5 vin3a_d5 - -
B9 vout1_d22 2372 248 2745 127 CFG_VOUT1_D22_IN - vin4a_d6 vin3a_d6 - -
A10 vout1_d23 2088 392 2608 124 CFG_VOUT1_D23_IN - vin4a_d7 vin3a_d7 - -
G11 vout1_d3 2475 523 2771 475 CFG_VOUT1_D3_IN - vin4a_d19 vin3a_d19 - -
E9 vout1_d4 2481 458 2772 410 CFG_VOUT1_D4_IN - vin4a_d20 vin3a_d20 - -
F9 vout1_d5 2335 451 2711 328 CFG_VOUT1_D5_IN - vin4a_d21 vin3a_d21 - -
F8 vout1_d6 2485 461 2739 459 CFG_VOUT1_D6_IN - vin4a_d22 vin3a_d22 - -
E7 vout1_d7 2496 514 2767 495 CFG_VOUT1_D7_IN - vin4a_d23 vin3a_d23 - -
E8 vout1_d8 2459 492 2789 414 CFG_VOUT1_D8_IN - vin4a_d8 vin3a_d8 - -
D9 vout1_d9 2463 532 2790 441 CFG_VOUT1_D9_IN - vin4a_d9 vin3a_d9 - -
B10 vout1_de 2326 134 2713 0 CFG_VOUT1_DE_IN - vin4a_de0 vin3a_de0 - -
B11 vout1_fld 0 0 0 0 CFG_VOUT1_FLD_IN - vin4a_clk0 vin3a_clk0 - -
C11 vout1_hsync 2058 180 2456 0 CFG_VOUT1_HSYNC_IN - vin4a_hsync0 vin3a_hsync0 - -
E11 vout1_vsync 2226 18 2332 0 CFG_VOUT1_VSYNC_IN - vin4a_vsync0 vin3a_vsync0 - -

Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-41, Manual Functions Mapping for VIP2 4A for a definition of the Manual modes.

Table 5-41 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-41 Manual Functions Mapping for VIP2 4A

BALL BALL NAME VIP2_4A_MANUAL1 VIP2_4A_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 3 4 5
R6 gpmc_a0 2108 183 2229 0 CFG_GPMC_A0_IN - vin4a_d0 -
T9 gpmc_a1 1977 152 2082 0 CFG_GPMC_A1_IN - vin4a_d1 -
P9 gpmc_a11 1973 0 1964 0 CFG_GPMC_A11_IN - vin4a_fld0 -
P4 gpmc_a12 0 0 0 0 CFG_GPMC_A12_IN - vin4a_clk0 -
R3 gpmc_a13 2042 263 2251 0 CFG_GPMC_A13_IN - vin4a_hsync0 -
T2 gpmc_a14 2124 726 2678 158 CFG_GPMC_A14_IN - vin4a_vsync0 -
U2 gpmc_a15 1922 307 2226 0 CFG_GPMC_A15_IN - vin4a_d8 -
U1 gpmc_a16 2082 318 2340 0 CFG_GPMC_A16_IN - vin4a_d9 -
P3 gpmc_a17 1987 328 2216 0 CFG_GPMC_A17_IN - vin4a_d10 -
R2 gpmc_a18 1428 0 1323 0 CFG_GPMC_A18_IN - vin4a_d11 -
K7 gpmc_a19 1755 0 1599 0 CFG_GPMC_A19_IN - vin4a_d12 -
T6 gpmc_a2 2202 359 2518 0 CFG_GPMC_A2_IN - vin4a_d2 -
M7 gpmc_a20 1561 0 1394 0 CFG_GPMC_A20_IN - vin4a_d13 -
J5 gpmc_a21 1795 41 1665 0 CFG_GPMC_A21_IN - vin4a_d14 -
K6 gpmc_a22 1637 0 1454 0 CFG_GPMC_A22_IN - vin4a_d15 -
J7 gpmc_a23 1489 0 1492 0 CFG_GPMC_A23_IN - vin4a_fld0 -
T7 gpmc_a3 2131 389 2502 0 CFG_GPMC_A3_IN - vin4a_d3 -
P6 gpmc_a4 2179 275 2403 0 CFG_GPMC_A4_IN - vin4a_d4 -
R9 gpmc_a5 2013 281 2248 0 CFG_GPMC_A5_IN - vin4a_d5 -
R5 gpmc_a6 1989 0 1920 0 CFG_GPMC_A6_IN - vin4a_d6 -
P5 gpmc_a7 2338 106 2348 0 CFG_GPMC_A7_IN - vin4a_d7 -
N1 gpmc_advn_ale 1960 0 1927 0 CFG_GPMC_ADVN_ALE_IN - vin4a_vsync0 -
P7 gpmc_clk 1941 0 1901 0 CFG_GPMC_CLK_IN - vin4a_hsync0 vin4a_de0
H6 gpmc_cs1 1412 0 1282 0 CFG_GPMC_CS1_IN - vin4a_de0 -
D11 vout1_clk 2425 88 2765 20 CFG_VOUT1_CLK_IN vin4a_fld0 - -
F11 vout1_d0 2460 555 2772 515 CFG_VOUT1_D0_IN vin4a_d16 - -
G10 vout1_d1 2307 500 2725 354 CFG_VOUT1_D1_IN vin4a_d17 - -
D7 vout1_d10 2367 275 2755 160 CFG_VOUT1_D10_IN vin4a_d10 - -
D8 vout1_d11 2480 337 2788 301 CFG_VOUT1_D11_IN vin4a_d11 - -
A5 vout1_d12 2344 290 2744 162 CFG_VOUT1_D12_IN vin4a_d12 - -
C6 vout1_d13 2381 184 2779 56 CFG_VOUT1_D13_IN vin4a_d13 - -
C8 vout1_d14 2459 533 2752 512 CFG_VOUT1_D14_IN vin4a_d14 - -
C7 vout1_d15 2386 263 2811 111 CFG_VOUT1_D15_IN vin4a_d15 - -
B7 vout1_d16 2378 197 2705 142 CFG_VOUT1_D16_IN vin4a_d0 - -
B8 vout1_d17 2538 171 2837 133 CFG_VOUT1_D17_IN vin4a_d1 - -
A7 vout1_d18 2433 69 2749 25 CFG_VOUT1_D18_IN vin4a_d2 - -
A8 vout1_d19 2158 0 2412 0 CFG_VOUT1_D19_IN vin4a_d3 - -
F10 vout1_d2 2401 291 2753 211 CFG_VOUT1_D2_IN vin4a_d18 - -
C9 vout1_d20 2361 401 2741 295 CFG_VOUT1_D20_IN vin4a_d4 - -
A9 vout1_d21 2181 0 2454 0 CFG_VOUT1_D21_IN vin4a_d5 - -
B9 vout1_d22 2276 0 2548 0 CFG_VOUT1_D22_IN vin4a_d6 - -
A10 vout1_d23 2070 274 2591 26 CFG_VOUT1_D23_IN vin4a_d7 - -
G11 vout1_d3 2419 403 2749 341 CFG_VOUT1_D3_IN vin4a_d19 - -
E9 vout1_d4 2465 311 2754 294 CFG_VOUT1_D4_IN vin4a_d20 - -
F9 vout1_d5 2306 319 2696 201 CFG_VOUT1_D5_IN vin4a_d21 - -
F8 vout1_d6 2450 312 2716 318 CFG_VOUT1_D6_IN vin4a_d22 - -
E7 vout1_d7 2477 403 2747 405 CFG_VOUT1_D7_IN vin4a_d23 - -
E8 vout1_d8 2407 425 2744 360 CFG_VOUT1_D8_IN vin4a_d8 - -
D9 vout1_d9 2512 277 2783 278 CFG_VOUT1_D9_IN vin4a_d9 - -
B10 vout1_de 2266 36 2576 0 CFG_VOUT1_DE_IN vin4a_de0 - -
B11 vout1_fld 0 0 0 0 CFG_VOUT1_FLD_IN vin4a_clk0 - -
C11 vout1_hsync 2016 50 2300 0 CFG_VOUT1_HSYNC_IN vin4a_hsync0 - -
E11 vout1_vsync 1953 0 2088 0 CFG_VOUT1_VSYNC_IN vin4a_vsync0 - -

Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-42, Manual Functions Mapping for VIP2 4A IOSET3 for a definition of the Manual modes.

Table 5-42 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-42 Manual Functions Mapping for VIP2 4A IOSET3

BALL BALL NAME VIP2_4A_IOSET3_MANUAL1 VIP2_4A_IOSET3_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 8
E21 gpio6_14 599 0 901 0 CFG_GPIO6_14_IN vin4a_hsync0
F20 gpio6_15 1291 0 1593 0 CFG_GPIO6_15_IN vin4a_vsync0
F21 gpio6_16 926 0 1228 0 CFG_GPIO6_16_IN vin4a_fld0
B14 mcasp1_aclkr 1768 0 2071 0 CFG_MCASP1_ACLKR_IN vin4a_d0
G13 mcasp1_axr2 2326 851 2737 792 CFG_MCASP1_AXR2_IN vin4a_d2
J11 mcasp1_axr3 2406 562 2858 434 CFG_MCASP1_AXR3_IN vin4a_d3
E12 mcasp1_axr4 2219 678 2742 464 CFG_MCASP1_AXR4_IN vin4a_d4
F13 mcasp1_axr5 2226 676 2728 517 CFG_MCASP1_AXR5_IN vin4a_d5
C12 mcasp1_axr6 2265 510 2806 271 CFG_MCASP1_AXR6_IN vin4a_d6
D12 mcasp1_axr7 2302 781 2708 726 CFG_MCASP1_AXR7_IN vin4a_d7
J14 mcasp1_fsr 1901 184 2386 0 CFG_MCASP1_FSR_IN vin4a_d1
E15 mcasp2_aclkr 1555 0 1857 0 CFG_MCASP2_ACLKR_IN vin4a_d8
B15 mcasp2_axr0 1790 658 2407 343 CFG_MCASP2_AXR0_IN vin4a_d10
A15 mcasp2_axr1 1939 279 2527 0 CFG_MCASP2_AXR1_IN vin4a_d11
D15 mcasp2_axr4 1924 369 2541 53 CFG_MCASP2_AXR4_IN vin4a_d12
B16 mcasp2_axr5 1719 400 2337 84 CFG_MCASP2_AXR5_IN vin4a_d13
B17 mcasp2_axr6 1116 0 1418 0 CFG_MCASP2_AXR6_IN vin4a_d14
A17 mcasp2_axr7 1477 362 2094 47 CFG_MCASP2_AXR7_IN vin4a_d15
A20 mcasp2_fsr 1521 8 1830 0 CFG_MCASP2_FSR_IN vin4a_d9
C18 mcasp4_aclkx 1258 0 1418 0 CFG_MCASP4_ACLKX_IN vin4a_d16
G16 mcasp4_axr0 2334 227 2813 26 CFG_MCASP4_AXR0_IN vin4a_d18
D17 mcasp4_axr1 2334 529 2777 437 CFG_MCASP4_AXR1_IN vin4a_d19
A21 mcasp4_fsx 2293 0 2570 0 CFG_MCASP4_FSX_IN vin4a_d17
AA3 mcasp5_aclkx 3053 2527 3352 2409 CFG_MCASP5_ACLKX_IN vin4a_d20
AB3 mcasp5_axr0 3058 3254 3315 3285 CFG_MCASP5_AXR0_IN vin4a_d22
AA4 mcasp5_axr1 3090 3358 3331 3446 CFG_MCASP5_AXR1_IN vin4a_d23
AB9 mcasp5_fsx 3060 2699 3329 2686 CFG_MCASP5_FSX_IN vin4a_d21
B26 xref_clk2 0 0 0 0 CFG_XREF_CLK2_IN vin4a_clk0
C23 xref_clk3 962 0 1265 0 CFG_XREF_CLK3_IN vin4a_de0

Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-43, Manual Functions Mapping for VIP2 4B for a definition of the Manual modes.

Table 5-43 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-43 Manual Functions Mapping for VIP2 4B

BALL BALL NAME VIP2_4B_MANUAL1 VIP2_4B_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 5 6
R6 gpmc_a0 2199 621 2416 398 CFG_GPMC_A0_IN - vin4b_d0
T9 gpmc_a1 1989 612 2267 323 CFG_GPMC_A1_IN - vin4b_d1
N9 gpmc_a10 0 0 0 0 CFG_GPMC_A10_IN - vin4b_clk1
P9 gpmc_a11 2133 859 2303 720 CFG_GPMC_A11_IN - vin4b_de1
P4 gpmc_a12 2258 562 2399 393 CFG_GPMC_A12_IN - vin4b_fld1
T6 gpmc_a2 2218 912 2365 720 CFG_GPMC_A2_IN - vin4b_d2
T7 gpmc_a3 2168 963 2341 781 CFG_GPMC_A3_IN - vin4b_d3
P6 gpmc_a4 2196 813 2362 594 CFG_GPMC_A4_IN - vin4b_d4
R9 gpmc_a5 2082 782 2329 525 CFG_GPMC_A5_IN - vin4b_d5
R5 gpmc_a6 2098 407 2320 171 CFG_GPMC_A6_IN - vin4b_d6
P5 gpmc_a7 2343 585 2522 305 CFG_GPMC_A7_IN - vin4b_d7
N7 gpmc_a8 2030 685 2290 284 CFG_GPMC_A8_IN - vin4b_hsync1
R4 gpmc_a9 2116 832 2335 548 CFG_GPMC_A9_IN - vin4b_vsync1
U4 mdio_d 1860 189 2164 0 CFG_MDIO_D_IN vin4b_d0 -
V1 mdio_mclk 0 0 0 0 CFG_MDIO_MCLK_IN vin4b_clk1 -
U5 rgmii0_rxc 1965 550 2306 279 CFG_RGMII0_RXC_IN vin4b_d5 -
V5 rgmii0_rxctl 1911 605 2235 369 CFG_RGMII0_RXCTL_IN vin4b_d6 -
W2 rgmii0_rxd0 1954 304 2294 26 CFG_RGMII0_RXD0_IN vin4b_fld1 -
V4 rgmii0_rxd3 1925 835 2252 613 CFG_RGMII0_RXD3_IN vin4b_d7 -
W9 rgmii0_txc 1937 849 2291 633 CFG_RGMII0_TXC_IN vin4b_d3 -
V9 rgmii0_txctl 1997 872 2272 744 CFG_RGMII0_TXCTL_IN vin4b_d4 -
V6 rgmii0_txd1 1989 771 2264 643 CFG_RGMII0_TXD1_IN vin4b_vsync1 -
U7 rgmii0_txd2 1788 682 2193 334 CFG_RGMII0_TXD2_IN vin4b_hsync1 -
V7 rgmii0_txd3 2091 591 2345 411 CFG_RGMII0_TXD3_IN vin4b_de1 -
V2 uart3_rxd 1711 0 1699 0 CFG_UART3_RXD_IN vin4b_d1 -
Y1 uart3_txd 1830 318 2176 0 CFG_UART3_TXD_IN vin4b_d2 -

Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-44, Manual Functions Mapping for VIP2 3B IOSET2 for a definition of the Manual modes.

Table 5-44 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-44 Manual Functions Mapping for VIP2 3B IOSET2

BALL BALL NAME VIP2_3B_IOSET2_MANUAL1 VIP2_3B_IOSET2_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 4 6
K7 gpmc_a19 1801 826 2145 501 CFG_GPMC_A19_IN - vin3b_d0
M7 gpmc_a20 1706 697 2037 373 CFG_GPMC_A20_IN - vin3b_d1
J5 gpmc_a21 1767 937 2101 612 CFG_GPMC_A21_IN - vin3b_d2
K6 gpmc_a22 1678 895 1998 584 CFG_GPMC_A22_IN - vin3b_d3
J7 gpmc_a23 1680 769 2016 619 CFG_GPMC_A23_IN - vin3b_d4
J4 gpmc_a24 1585 1015 1931 690 CFG_GPMC_A24_IN - vin3b_d5
J6 gpmc_a25 1643 893 2001 531 CFG_GPMC_A25_IN - vin3b_d6
H4 gpmc_a26 1627 958 1978 586 CFG_GPMC_A26_IN - vin3b_d7
H5 gpmc_a27 1709 686 2036 412 CFG_GPMC_A27_IN - vin3b_hsync1
N6 gpmc_ben0 1993 579 2297 340 CFG_GPMC_BEN0_IN - vin3b_de1
M4 gpmc_ben1 0 0 0 0 CFG_GPMC_BEN1_IN vin3b_clk1 vin3b_fld1
H6 gpmc_cs1 1492 850 1829 486 CFG_GPMC_CS1_IN - vin3b_vsync1