SPRS950F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
TI recommends that a PDN/power integrity analysis is performed to ensure that capacitor selection and placement is optimal for a given implementation. This section provides guidelines that can serve as a good starting point.
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power, and processor/DDR ground connections. Table 8-36 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
HS21 | HS bypass capacitor package size(1) | 0201 | 0402 | 10 Mils | |
HS22 | Distance, HS bypass capacitor to processor being bypassed(2)(3)(4) | 400(12) | Mils | ||
HS23 | processor HS bypass capacitor count per vdds_ddrx rail (12) | See Table 8-3 and (11) | Devices | ||
HS24 | processor vdds_ddrx HS bypass capacitor total capacitance (12) | See Table 8-3 and (11) | μF | ||
HS25 | Number of connection vias for each device power/ground ball(5) | 1 | Vias | ||
HS26 | Trace length from device power/ground ball to connection via(2) | 35 | 70 | Mils | |
HS27 | Distance, HS bypass capacitor to DDR device being bypassed(6) | 150 | Mils | ||
HS28 | Number of connection vias for each HS capacitor(8)(9) | 4 (14) | Vias | ||
HS29 | DDR2 device HS bypass capacitor count(7) | 12 (13) | Devices | ||
HS210 | DDR2 device HS bypass capacitor total capacitance(7) | 0.85 | μF | ||
HS211 | Trace length from bypass capacitor connect to connection via(2)(9) | 35 | 100 | Mils | |
HS212 | Number of connection vias for each DDR2 device power/ground ball(10) | 1 | Vias | ||
HS213 | Trace length from DDR2 device power/ground ball to connection via(2)(8) | 35 | 60 | Mils |