SPRS950F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Figure 7-83, Figure 7-84, and Table 7-125 through Table 7-128 present Timing requirements and Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmitter mode.
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
DS5 | tsu(cmdV-clkH) | Setup time, mmc3_cmd valid before mmc3_clk rising clock edge | 5.11 | ns | |
DS6 | th(clkH-cmdV) | Hold time, mmc3_cmd valid after mmc3_clk rising clock edge | 20.46 | ns | |
DS7 | tsu(dV-clkH) | Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge | 5.11 | ns | |
DS8 | th(clkH-dV) | Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge | 20.46 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
DS0 | fop(clk) | Operating frequency, mmc3_clk | 24 | MHz | |
DS1 | tw(clkH) | Pulse duration, mmc3_clk high | 0.5*P-0.270 (1) | ns | |
DS2 | tw(clkL) | Pulse duration, mmc3_clk low | 0.5*P-0.270 (1) | ns | |
DS3 | td(clkL-cmdV) | Delay time, mmc3_clk falling clock edge to mmc3_cmd transition | -14.93 | 14.93 | ns |
DS4 | td(clkL-dV) | Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition | -14.93 | 14.93 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
DS5 | tsu(cmdV-clkH) | Setup time, mmc4_cmd valid before mmc4_clk rising clock edge | 5.11 | ns | |
DS6 | th(clkH-cmdV) | Hold time, mmc4_cmd valid after mmc4_clk rising clock edge | 20.46 | ns | |
DS7 | tsu(dV-clkH) | Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge | 5.11 | ns | |
DS8 | th(clkH-dV) | Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge | 20.46 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
DS0 | fop(clk) | Operating frequency, mmc4_clk | 24 | MHz | |
DS1 | tw(clkH) | Pulse duration, mmc4_clk high | 0.5*P-0.270 (1) | ns | |
DS2 | tw(clkL) | Pulse duration, mmc4_clk low | 0.5*P-0.270 (1) | ns | |
DS3 | td(clkL-cmdV) | Delay time, mmc4_clk falling clock edge to mmc4_cmd transition | -14.93 | 14.93 | ns |
DS4 | td(clkL-dV) | Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition | -14.93 | 14.93 | ns |