SPRS950F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1, SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
NOTE
For more information, see the Serial Communication Interface section of the device TRM.
NOTE
The McSPIm module (m = 1 to 4) is also referred to as SPIm.
CAUTION
The IO timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are only valid for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETS are defined in the Table 7-45.
Table 7-43, Figure 7-33 and Figure 7-34 present Timing Requirements for McSPI - Master Mode.
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
SM1 | tc(SPICLK) | Cycle time, spi_sclk (1)(2) | SPI1/2/3/4 | 20.8 (3) | ns | |
SM2 | tw(SPICLKL) | Typical Pulse duration, spi_sclk low (1) | 0.5*P-1 (4) | ns | ||
SM3 | tw(SPICLKH) | Typical Pulse duration, spi_sclk high (1) | 0.5*P-1 (4) | ns | ||
SM4 | tsu(MISO-SPICLK) | Setup time, spi_d[x] valid before spi_sclk active edge (1) | 4.4 | ns | ||
SM5 | th(SPICLK-MISO) | Hold time, spi_d[x] valid after spi_sclk active edge (1) | 3.9 | ns | ||
SM6 | td(SPICLK-SIMO) | Delay time, spi_sclk active edge to spi_d[x] transition (1) | SPI1 | -4.27 | 4.27 | ns |
SPI2 | -4.32 | 4.32 | ns | |||
SPI3 | -5.37 | 4.23 | ns | |||
SPI4 | -3.81 | 4..41 | ns | |||
SM7 | td(CS-SIMO) | Delay time, spi_cs[x] active edge to spi_d[x] transition | 5 | ns | ||
SM8 | td(CS-SPICLK) | Delay time, spi_cs[x] active to spi_sclk first edge (1) | MASTER_PHA0 (5) | B-4.6 (6) | ns | |
MASTER_PHA1 (5) | A-4.6 (7) | ns | ||||
SM9 | td(SPICLK-CS) | Delay time, spi_sclk last edge to spi_cs[x] inactive (1) | MASTER_PHA0 (5) | A-4.6 (7) | ns | |
MASTER_PHA1 (5) | B-4.6 (6) | ns |
Table 7-44, Figure 7-35 and Figure 7-36 present Timing Requirements for McSPI - Slave Mode.
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
SS1 | tc(SPICLK) | Cycle time, spi_sclk (1)(2) | (3) | 62.5 | ns | |
SS2 | tw(SPICLKL) | Typical Pulse duration, spi_sclk low (1) | 0.45*P (4) | ns | ||
SS3 | tw(SPICLKH) | Typical Pulse duration, spi_sclk high (1) | 0.45*P (4) | ns | ||
SS4 | tsu(SIMO-SPICLK) | Setup time, spi_d[x] valid before spi_sclk active edge (1) | 5 | ns | ||
SS5 | th(SPICLK-SIMO) | Hold time, spi_d[x] valid after spi_sclk active edge (1) | 5 | ns | ||
SS6 | td(SPICLK-SOMI) | Delay time, spi_sclk active edge to mcspi_somi transition (1) | SPI1/2/3 | 2 | 26.1 | ns |
SPI4 | 2 | 18 | ns | |||
SS7 | td(CS-SOMI) | Delay time, spi_cs[x] active edge to mcspi_somi transition (1) | 20.95 | ns | ||
SS8 | tsu(CS-SPICLK) | Setup time, spi_cs[x] valid before spi_sclk first edge (1) | 5 | ns | ||
SS9 | th(SPICLK-CS) | Hold time, spi_cs[x] valid after spi_sclk last edge (1) | 5 | ns |
In Table 7-45 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4.
Signal | IOSET1 | IOSET2 | IOSET3 | IOSET4 | IOSET5 | IOSET6 | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
BALL | MUX | BALL | MUX | BALL | MUX | BALL | MUX | BALL | MUX | BALL | MUX | |
SPI3 | ||||||||||||
spi3_sclk | AD9 | 8 | E11 | 8 | V2 | 7 | B12 | 3 | C18 | 2 | AC4 | 1 |
spi3_d1 | AF9 | 8 | B10 | 8 | Y1 | 7 | A11 | 3 | A21 | 2 | AC7 | 1 |
spi3_d0 | AE9 | 8 | C11 | 8 | W9 | 7 | B13 | 3 | G16 | 2 | AC6 | 1 |
spi3_cs0 | AF8 | 8 | D11 | 8 | V9 | 7 | A12 | 3 | D17 | 2 | AC9 | 1 |
spi3_cs1 | AC3 | 1 | B11 | 8 | AC3 | 1 | E14 | 3 | B11 | 8 | AC3 | 1 |
spi3_cs2 | - | - | F11 | 8 | - | - | F11 | 8 | F11 | 8 | - | - |
spi3_cs3 | - | - | A10 | 8 | - | - | A10 | 8 | A10 | 8 | - | - |
SPI4 | ||||||||||||
spi4_sclk | N7 | 8 | G1 | 8 | V7 | 7 | AA3 | 2 | AC8 | 1 | - | - |
spi4_d1 | R4 | 8 | G6 | 8 | U7 | 7 | AB9 | 2 | AD6 | 1 | - | - |
spi4_d0 | N9 | 8 | F2 | 8 | V6 | 7 | AB3 | 2 | AB8 | 1 | - | - |
spi4_cs0 | P9 | 8 | F3 | 8 | U6 | 7 | AA4 | 2 | AB5 | 1 | - | - |
spi4_cs1 | P4 | 8 | P4 | 8 | Y1 | 8 | Y1 | 8 | Y1 | 8 | - | - |
spi4_cs2 | R3 | 8 | R3 | 8 | W9 | 8 | W9 | 8 | W9 | 8 | - | - |
spi4_cs3 | T2 | 8 | T2 | 8 | V9 | 8 | V9 | 8 | V9 | 8 | - | - |