SPRS950F December   2015  – May 2019 DRA745 , DRA746 , DRA750 , DRA756

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  External Memory Interface (EMIF)
      5. 4.4.5  General-Purpose Memory Controller (GPMC)
      6. 4.4.6  Timers
      7. 4.4.7  Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8  HDQ / 1-Wire Interface (HDQ1W)
      9. 4.4.9  Universal Asynchronous Receiver Transmitter (UART)
      10. 4.4.10 Multichannel Serial Peripheral Interface (McSPI)
      11. 4.4.11 Quad Serial Peripheral Interface (QSPI)
      12. 4.4.12 Multichannel Audio Serial Port (McASP)
      13. 4.4.13 Universal Serial Bus (USB)
      14. 4.4.14 SATA
      15. 4.4.15 Peripheral Component Interconnect Express (PCIe)
      16. 4.4.16 Controller Area Network Interface (DCAN)
      17. 4.4.17 Ethernet Interface (GMAC_SW)
      18. 4.4.18 Media Local Bus (MLB) Interface
      19. 4.4.19 eMMC/SD/SDIO
      20. 4.4.20 General-Purpose Interface (GPIO)
      21. 4.4.21 Keyboard controller (KBD)
      22. 4.4.22 Pulse Width Modulation (PWM) Interface
      23. 4.4.23 Audio Tracking Logic (ATL)
      24. 4.4.24 Test Interfaces
      25. 4.4.25 System and Miscellaneous
        1. 4.4.25.1 Sysboot
        2. 4.4.25.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.25.3 Real Time Clock (RTC) Interface
        4. 4.4.25.4 System Direct Memory Access (SDMA)
        5. 4.4.25.5 Interrupt Controllers (INTC)
        6. 4.4.25.6 Observability
      26. 4.4.26 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  ILVDS18 Buffers DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 PCIEPHY DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 RC On-die Oscillator Clock
    3. 6.3 DPLLs, DLLs Specifications
      1. 6.3.1 DPLL Characteristics
      2. 6.3.2 DLL Characteristics
      3. 6.3.3 DPLL and DLL Noise Isolation
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem – Video Output Ports
    8. 7.8  Display Subsystem – High-Definition Multimedia Interface (HDMI)
    9. 7.9  External Memory Interface (EMIF)
    10. 7.10 General-Purpose Memory Controller (GPMC)
      1. 7.10.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11 Timers
    12. 7.12 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-34 Timing Requirements for I2C Input Timings
      2. Table 7-35 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-36 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    13. 7.13 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.13.1 HDQ / 1-Wire — HDQ Mode
      2. 7.13.2 HDQ/1-Wire—1-Wire Mode
    14. 7.14 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-41 Timing Requirements for UART
      2. Table 7-42 Switching Characteristics Over Recommended Operating Conditions for UART
    15. 7.15 Multichannel Serial Peripheral Interface (McSPI)
    16. 7.16 Quad Serial Peripheral Interface (QSPI)
    17. 7.17 Multichannel Audio Serial Port (McASP)
      1. Table 7-49 Timing Requirements for McASP1
      2. Table 7-50 Timing Requirements for McASP2
      3. Table 7-51 Timing Requirements for McASP3/4/5/6/7/8
      4. Table 7-52 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-53 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-54 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
    18. 7.18 Universal Serial Bus (USB)
      1. 7.18.1 USB1 DRD PHY
      2. 7.18.2 USB2 PHY
      3. 7.18.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
    19. 7.19 Serial Advanced Technology Attachment (SATA)
    20. 7.20 Peripheral Component Interconnect Express (PCIe)
    21. 7.21 Controller Area Network Interface (DCAN)
      1. Table 7-69 Timing Requirements for DCANx Receive
      2. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    22. 7.22 Ethernet Interface (GMAC_SW)
      1. 7.22.1 GMAC MII Timings
        1. Table 7-71 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-72 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-73 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-74 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.22.2 GMAC MDIO Interface Timings
      3. 7.22.3 GMAC RMII Timings
        1. Table 7-79 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-80 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-81 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-82 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.22.4 GMAC RGMII Timings
        1. Table 7-86 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-87 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-88 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-89 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    23. 7.23 Media Local Bus (MLB) interface
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1—SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 — eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.24.3 MMC3 and MMC4—SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 Audio Tracking Logic (ATL)
      1. 7.26.1 ATL Electrical Data/Timing
        1. Table 7-145 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
          1. Table 7-146 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-147 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-148 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-149 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Introduction
      1. 8.1.1 Initial Requirements and Guidelines
    2. 8.2 Power Optimizations
      1. 8.2.1 Step 1: PCB Stack-up
      2. 8.2.2 Step 2: Physical Placement
      3. 8.2.3 Step 3: Static Analysis
        1. 8.2.3.1 PDN Resistance and IR Drop
      4. 8.2.4 Step 4: Frequency Analysis
      5. 8.2.5 System ESD Generic Guidelines
        1. 8.2.5.1 System ESD Generic PCB Guideline
        2. 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 8.2.6 EMI / EMC Issues Prevention
        1. 8.2.6.1 Signal Bandwidth
        2. 8.2.6.2 Signal Routing
          1. 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 8.2.6.3 Ground Guidelines
          1. 8.2.6.3.1 PCB Outer Layers
          2. 8.2.6.3.2 Metallic Frames
          3. 8.2.6.3.3 Connectors
          4. 8.2.6.3.4 Guard Ring on PCB Edges
          5. 8.2.6.3.5 Analog and Digital Ground
    3. 8.3 Core Power Domains
      1. 8.3.1 General Constraints and Theory
      2. 8.3.2 Voltage Decoupling
      3. 8.3.3 Static PDN Analysis
      4. 8.3.4 Dynamic PDN Analysis
      5. 8.3.5 Power Supply Mapping
      6. 8.3.6 DPLL Voltage Requirement
      7. 8.3.7 Loss of Input Power Event
      8. 8.3.8 Example PCB Design
        1. 8.3.8.1 Example Stack-up
        2. 8.3.8.2 vdd_mpu Example Analysis
    4. 8.4 Single-Ended Interfaces
      1. 8.4.1 General Routing Guidelines
      2. 8.4.2 QSPI Board Design and Layout Guidelines
    5. 8.5 Differential Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1 Background
        2. 8.5.2.2 USB PHY Layout Guide
          1. 8.5.2.2.1 General Routing and Placement
          2. 8.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3  Board Stackup
            4. 8.5.2.2.2.4  Cable Connector Socket
            5. 8.5.2.2.2.5  Clock Routings
            6. 8.5.2.2.2.6  Crystals/Oscillator
            7. 8.5.2.2.2.7  DP/DM Trace
            8. 8.5.2.2.2.8  DP/DM Vias
            9. 8.5.2.2.2.9  Image Planes
            10. 8.5.2.2.2.10 JTAG Interface
            11. 8.5.2.2.2.11 Power Regulators
        3. 8.5.2.3 Electrostatic Discharge (ESD)
          1. 8.5.2.3.1 IEC ESD Stressing Test
            1. 8.5.2.3.1.1 Test Mode
            2. 8.5.2.3.1.2 Air Discharge Mode
            3. 8.5.2.3.1.3 Test Type
          2. 8.5.2.3.2 TI Component Level IEC ESD Test
          3. 8.5.2.3.3 Construction of a Custom USB Connector
          4. 8.5.2.3.4 ESD Protection System Design Consideration
        4. 8.5.2.4 References
      3. 8.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1 USB 3.0 interface introduction
        2. 8.5.3.2 USB 3.0 General routing rules
      4. 8.5.4 HDMI Board Design and Layout Guidelines
        1. 8.5.4.1 HDMI Interface Schematic
        2. 8.5.4.2 TMDS General Routing Guidelines
        3. 8.5.4.3 TPD5S115
        4. 8.5.4.4 HDMI ESD Protection Device (Required)
        5. 8.5.4.5 PCB Stackup Specifications
        6. 8.5.4.6 Grounding
      5. 8.5.5 SATA Board Design and Layout Guidelines
        1. 8.5.5.1 SATA Interface Schematic
        2. 8.5.5.2 Compatible SATA Components and Modes
        3. 8.5.5.3 PCB Stackup Specifications
        4. 8.5.5.4 Routing Specifications
      6. 8.5.6 PCIe Board Design and Layout Guidelines
        1. 8.5.6.1 PCIe Connections and Interface Compliance
          1. 8.5.6.1.1 Coupling Capacitors
          2. 8.5.6.1.2 Polarity Inversion
        2. 8.5.6.2 Non-standard PCIe connections
          1. 8.5.6.2.1 PCB Stackup Specifications
          2. 8.5.6.2.2 Routing Specifications
            1. 8.5.6.2.2.1 Impedance
            2. 8.5.6.2.2.2 Differential Coupling
            3. 8.5.6.2.2.3 Pair Length Matching
        3. 8.5.6.3 LJCB_REFN/P Connections
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
    7. 8.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 8.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 8.7.2 DDR2 Board Design and Layout Guidelines
        1. 8.7.2.1 Board Designs
        2. 8.7.2.2 DDR2 Interface
          1. 8.7.2.2.1  DDR2 Interface Schematic
          2. 8.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 8.7.2.2.3  PCB Stackup
          4. 8.7.2.2.4  Placement
          5. 8.7.2.2.5  DDR2 Keepout Region
          6. 8.7.2.2.6  Bulk Bypass Capacitors
          7. 8.7.2.2.7  High-Speed Bypass Capacitors
          8. 8.7.2.2.8  Net Classes
          9. 8.7.2.2.9  DDR2 Signal Termination
          10. 8.7.2.2.10 VREF Routing
        3. 8.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 8.7.3 DDR3 Board Design and Layout Guidelines
        1. 8.7.3.1  Board Designs
          1. 8.7.3.1.1 DDR3 versus DDR2
        2. 8.7.3.2  DDR3 EMIFs
        3. 8.7.3.3  DDR3 Device Combinations
        4. 8.7.3.4  DDR3 Interface Schematic
          1. 8.7.3.4.1 32-Bit DDR3 Interface
          2. 8.7.3.4.2 16-Bit DDR3 Interface
        5. 8.7.3.5  Compatible JEDEC DDR3 Devices
        6. 8.7.3.6  PCB Stackup
        7. 8.7.3.7  Placement
        8. 8.7.3.8  DDR3 Keepout Region
        9. 8.7.3.9  Bulk Bypass Capacitors
        10. 8.7.3.10 High-Speed Bypass Capacitors
          1. 8.7.3.10.1 Return Current Bypass Capacitors
        11. 8.7.3.11 Net Classes
        12. 8.7.3.12 DDR3 Signal Termination
        13. 8.7.3.13 VREF_DDR Routing
        14. 8.7.3.14 VTT
        15. 8.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.3.15.1 Four DDR3 Devices
            1. 8.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.3.15.2 Two DDR3 Devices
            1. 8.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.3.15.3 One DDR3 Device
            1. 8.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.3.16 Data Topologies and Routing Definition
          1. 8.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.3.17 Routing Specification
          1. 8.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.7.3.17.2 DQS and DQ Routing Specification
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABC|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Video Input Ports (VIP)

The Device includes 3 Video Input Ports (VIP).

Table 7-3, Figure 7-4 and Figure 7-5 present timings and switching characteristics of the VIPs.

CAUTION

The IO timings provided in this section are applicable for all combinations of signals for vin1, vin5 and vin6. However, the timings are only valid for vin2, vin3, and vin4 if signals within a single IOSET are used. The IOSETs are defined in the Table 7-4, Table 7-5 and Table 7-6.

Table 7-3 Timing Requirements for VIP (1)(2)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
V1 tc(CLK) Cycle time, vinx_clki (3)(5) 6.06 (1) ns
V2 tw(CLKH) Pulse duration, vinx_clki high (3)(5) 0.45*P (2) ns
V3 tw(CLKL) Pulse duration, vinx_clki low (3)(5) 0.45*P (2) ns
V4 tsu(CTL/DATA-CLK) Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3)(4)(5) vin1x, vin2x 2.93 ns
vin5x, vin6x 3.11 ns
vin3x, vin4x 3.11 ns
V5 th(CLK-CTL/DATA) Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid from vinx_clki transition (3)(4)(5) -0.05 ns
  1. For maximum frequency of 165 MHZ.
  2. P = vinx_clki period.
  3. x in vinx = 1a, 1b, 2a, 2b, 3a, 3b, 4a, 4b, 5a and 6a.
  4. n in dn = 0 to 7 when x = 1b, 2b, 3b and 4b;
    n = 0 to 15 when x = 5a and 6a;
    n = 0 to 23 when x = 1a, 2a, 3a and 4a;
  5. i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 SPRS8xx_VIP_01.gifFigure 7-4 Video Input Ports clock signal
DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 SPRS8xx_VIP_02.gifFigure 7-5 Video Input Ports timings

In Table 7-4, Table 7-5 and Table 7-6 are presented the specific groupings of signals (IOSET) for use with vin2, vin3, and vin4.

Table 7-4 VIN2 IOSETs

Signals IOSET1 IOSET2 IOSET3
BALL MUX BALL MUX BALL MUX
vin2a
vin2a_d0 F2 0 F2 0 U4 4
vin2a_d1 F3 0 F3 0 V2 4
vin2a_d2 D1 0 D1 0 Y1 4
vin2a_d3 E2 0 E2 0 W9 4
vin2a_d4 D2 0 D2 0 V9 4
vin2a_d5 F4 0 F4 0 U5 4
vin2a_d6 C1 0 C1 0 V5 4
vin2a_d7 E4 0 E4 0 V4 4
vin2a_d8 F5 0 F5 0 V3 4
vin2a_d9 E6 0 E6 0 Y2 4
vin2a_d10 D3 0 D3 0 U6 4
vin2a_d11 F6 0 F6 0 U3 4
vin2a_d12 D5 0 D5 0 - -
vin2a_d13 C2 0 C2 0 - -
vin2a_d14 C3 0 C3 0 - -
vin2a_d15 C4 0 C4 0 - -
vin2a_d16 B2 0 B2 0 - -
vin2a_d17 D6 0 D6 0 - -
vin2a_d18 C5 0 C5 0 - -
vin2a_d19 A3 0 A3 0 - -
vin2a_d20 B3 0 B3 0 - -
vin2a_d21 B4 0 B4 0 - -
vin2a_d22 B5 0 B5 0 - -
vin2a_d23 A4 0 A4 0 - -
vin2a_hsync0 G1 0 G1 0 U7 4
vin2a_vsync0 G6 0 G6 0 V6 4
vin2a_de0 G2 0 - - V7 4
vin2a_fld0 H7 0 G2 1 W2 4
vin2a_clk0 E1 0 E1 0 V1 4
vin2b
vin2b_clk1 H7 2 H7 2 AB5 4
vin2b_de1 - - G2 3 AB8 4
vin2b_fld1 G2 2 - - - -
vin2b_d0 A4 2 A4 2 AD6 4
vin2b_d1 B5 2 B5 2 AC8 4
vin2b_d2 B4 2 B4 2 AC3 4
vin2b_d3 B3 2 B3 2 AC9 4
vin2b_d4 A3 2 A3 2 AC6 4
vin2b_d5 C5 2 C5 2 AC7 4
vin2b_d6 D6 2 D6 2 AC4 4
vin2b_d7 B2 2 B2 2 AD4 4
vin2b_hsync1 G1 3 G1 3 AC5 4
vin2b_vsync1 G6 3 G6 3 AB4 4

Table 7-5 VIN3 IOSETs

Signals IOSET1 IOSET2 IOSET3 IOSET4
BALL MUX BALL MUX BALL MUX BALL MUX
vin3a
vin3a_d0 M6 2 AF1 6 AF1 6 B7 4
vin3a_d1 M2 2 AE3 6 AE3 6 B8 4
vin3a_d2 L5 2 AE5 6 AE5 6 A7 4
vin3a_d3 M1 2 AE1 6 AE1 6 A8 4
vin3a_d4 L6 2 AE2 6 AE2 6 C9 4
vin3a_d5 L4 2 AE6 6 AE6 6 A9 4
vin3a_d6 L3 2 AD2 6 AD2 6 B9 4
vin3a_d7 L2 2 AD3 6 AD3 6 A10 4
vin3a_d8 L1 2 B2 6 B2 6 E8 4
vin3a_d9 K2 2 D6 6 D6 6 D9 4
vin3a_d10 J1 2 C5 6 C5 6 D7 4
vin3a_d11 J2 2 A3 6 A3 6 D8 4
vin3a_d12 H1 2 B3 6 - - A5 4
vin3a_d13 J3 2 B4 6 - - C6 4
vin3a_d14 H2 2 B5 6 - - C8 4
vin3a_d15 H3 2 A4 6 - - C7 4
vin3a_d16 R6 2 - - - - F11 4
vin3a_d17 T9 2 - - - - G10 4
vin3a_d18 T6 2 - - - - F10 4
vin3a_d19 T7 2 - - - - G11 4
vin3a_d20 P6 2 - - - - E9 4
vin3a_d21 R9 2 - - - - F9 4
vin3a_d22 R5 2 - - - - F8 4
vin3a_d23 P5 2 - - - - E7 4
vin3a_hsync0 N7 2 N7 2 B5 5 C11 4
vin3a_vsync0 R4 2 R4 2 A4 5 E11 4
vin3a_de0 N9 2 N9 2 B3 5 B10 4
vin3a_fld0 P9 2 P9 2 B4 5 D11 4
vin3a_clk0 P1 2 AH7 6 AH7 6 B11 4
vin3b
vin3b_clk1 P7 6 M4 4 - - - -
vin3b_de1 N6 6 N6 6 - - - -
vin3b_fld1 M4 6 - - - - - -
vin3b_d0 K7 6 K7 6 - - - -
vin3b_d1 M7 6 M7 6 - - - -
vin3b_d2 J5 6 J5 6 - - - -
vin3b_d3 K6 6 K6 6 - - - -
vin3b_d4 J7 6 J7 6 - - - -
vin3b_d5 J4 6 J4 6 - - - -
vin3b_d6 J6 6 J6 6 - - - -
vin3b_d7 H4 6 H4 6 - - - -
vin3b_hsync1 H5 6 H5 6 - - - -
vin3b_vsync1 H6 6 H6 6 - - - -

Table 7-6 VIN4 IOSETs

Signals IOSET1 IOSET2 IOSET3
BALL MUX BALL MUX BALL MUX
vin4a
vin4a_d0 R6 4 B7 3 B14 8
vin4a_d1 T9 4 B8 3 J14 8
vin4a_d2 T6 4 A7 3 G13 8
vin4a_d3 T7 4 A8 3 J11 8
vin4a_d4 P6 4 C9 3 E12 8
vin4a_d5 R9 4 A9 3 F13 8
vin4a_d6 R5 4 B9 3 C12 8
vin4a_d7 P5 4 A10 3 D12 8
vin4a_d8 U2 4 E8 3 E15 8
vin4a_d9 U1 4 D9 3 A20 8
vin4a_d10 P3 4 D7 3 B15 8
vin4a_d11 R2 4 D8 3 A15 8
vin4a_d12 K7 4 A5 3 D15 8
vin4a_d13 M7 4 C6 3 B16 8
vin4a_d14 J5 4 C8 3 B17 8
vin4a_d15 K6 4 C7 3 A17 8
vin4a_d16 - - F11 3 C18 8
vin4a_d17 - - G10 3 A21 8
vin4a_d18 - - F10 3 G16 8
vin4a_d19 - - G11 3 D17 8
vin4a_d20 - - E9 3 AA3 8
vin4a_d21 - - F9 3 AB9 8
vin4a_d22 - - F8 3 AB3 8
vin4a_d23 - - E7 3 AA4 8
vin4a_hsync0 R3/P7 4 / 4 C11 3 E21 8
vin4a_vsync0 T2/N1 4 / 4 E11 3 F20 8
vin4a_de0 H6/P7 4 / 5 B10 3 C23 8
vin4a_fld0 P9/J7 4 / 4 D11 3 F21 8
vin4a_clk0 P4 4 B11 3 B26 8
vin4b
vin4b_clk1 N9 6 V1 5 - -
vin4b_de1 P9 6 V7 5 - -
vin4b_fld1 P4 6 W2 5 - -
vin4b_d0 R6 6 U4 5 - -
vin4b_d1 T9 6 V2 5 - -
vin4b_d2 T6 6 Y1 5 - -
vin4b_d3 T7 6 W9 5 - -
vin4b_d4 P6 6 V9 5 - -
vin4b_d5 R9 6 U5 5 - -
vin4b_d6 R5 6 V5 5 - -
vin4b_d7 P5 6 V4 5 - -
vin4b_hsync1 N7 6 U7 5 - -
vin4b_vsync1 R4 6 V6 5 - -


NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-7Manual Functions Mapping for VIP1 for a definition of the Manual modes.

Table 7-7 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-7 Manual Functions Mapping for VIP1

BALL BALL NAME VIP1_MANUAL1 VIP1_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 0 1 2 3 4
U3 RMII_MHZ_50_CLK 1621 614 2018 279 CFG_RMII_MHZ_50_CLK_IN - - - - vin2a_d11
N6 gpmc_ben0 1756 1019 2235 494 CFG_GPMC_BEN0_IN - - - vin1b_hsync1 -
M4 gpmc_ben1 1684 1107 2198 568 CFG_GPMC_BEN1_IN - - - vin1b_de1 -
U4 mdio_d 1594 417 2007 36 CFG_MDIO_D_IN - - - - vin2a_d0
V1 mdio_mclk 0 0 0 0 CFG_MDIO_MCLK_IN - - - - vin2a_clk0
U5 rgmii0_rxc 1005 935 1932 0 CFG_RGMII0_RXC_IN - - - - vin2a_d5
V5 rgmii0_rxctl 1579 836 1982 485 CFG_RGMII0_RXCTL_IN - - - - vin2a_d6
W2 rgmii0_rxd0 1032 1033 1995 0 CFG_RGMII0_RXD0_IN - - - - vin2a_fld0
Y2 rgmii0_rxd1 950 1625 1993 673 CFG_RGMII0_RXD1_IN - - - - vin2a_d9
V3 rgmii0_rxd2 1578 832 1973 535 CFG_RGMII0_RXD2_IN - - - - vin2a_d8
V4 rgmii0_rxd3 1022 1648 2017 740 CFG_RGMII0_RXD3_IN - - - - vin2a_d7
W9 rgmii0_txc 1604 769 2020 393 CFG_RGMII0_TXC_IN - - - - vin2a_d3
V9 rgmii0_txctl 1060 1389 2074 396 CFG_RGMII0_TXCTL_IN - - - - vin2a_d4
U6 rgmii0_txd0 938 1242 2021 194 CFG_RGMII0_TXD0_IN - - - - vin2a_d10
V6 rgmii0_txd1 1013 1679 2036 730 CFG_RGMII0_TXD1_IN - - - - vin2a_vsync0
U7 rgmii0_txd2 1524 886 1933 526 CFG_RGMII0_TXD2_IN - - - - vin2a_hsync0
V7 rgmii0_txd3 1079 1504 2090 490 CFG_RGMII0_TXD3_IN - - - - vin2a_de0
V2 uart3_rxd 1530 125 1586 0 CFG_UART3_RXD_IN - - - - vin2a_d1
Y1 uart3_txd 1572 487 1980 16 CFG_UART3_TXD_IN - - - - vin2a_d2
AG8 vin1a_clk0 0 0 0 0 CFG_VIN1A_CLK0_IN vin1a_clk0 - - - -
AE8 vin1a_d0 1697 1087 2105 619 CFG_VIN1A_D0_IN vin1a_d0 - - - -
AD8 vin1a_d1 1589 1164 2017 757 CFG_VIN1A_D1_IN vin1a_d1 - - - -
AG3 vin1a_d10 1733 1119 2107 739 CFG_VIN1A_D10_IN vin1a_d10 vin1b_d5 - - -
AG5 vin1a_d11 1563 1210 2005 788 CFG_VIN1A_D11_IN vin1a_d11 vin1b_d4 - - -
AF2 vin1a_d12 1705 1647 2059 1297 CFG_VIN1A_D12_IN vin1a_d12 vin1b_d3 - - -
AF6 vin1a_d13 1624 1525 2027 1141 CFG_VIN1A_D13_IN vin1a_d13 vin1b_d2 - - -
AF3 vin1a_d14 1730 1655 2071 1332 CFG_VIN1A_D14_IN vin1a_d14 vin1b_d1 - - -
AF4 vin1a_d15 1681 2004 1995 1764 CFG_VIN1A_D15_IN vin1a_d15 vin1b_d0 - - -
AF1 vin1a_d16 1659 1813 1999 1542 CFG_VIN1A_D16_IN vin1a_d16 vin1b_d7 - - -
AE3 vin1a_d17 1715 1887 2072 1540 CFG_VIN1A_D17_IN vin1a_d17 vin1b_d6 - - -
AE5 vin1a_d18 1728 1898 2034 1629 CFG_VIN1A_D18_IN vin1a_d18 vin1b_d5 - - -
AE1 vin1a_d19 1707 2006 2026 1761 CFG_VIN1A_D19_IN vin1a_d19 vin1b_d4 - - -
AG7 vin1a_d2 1557 1414 1996 962 CFG_VIN1A_D2_IN vin1a_d2 - - - -
AE2 vin1a_d20 1695 1814 2037 1469 CFG_VIN1A_D20_IN vin1a_d20 vin1b_d3 - - -
AE6 vin1a_d21 1757 1682 2077 1349 CFG_VIN1A_D21_IN vin1a_d21 vin1b_d2 - - -
AD2 vin1a_d22 1683 1813 2022 1545 CFG_VIN1A_D22_IN vin1a_d22 vin1b_d1 - - -
AD3 vin1a_d23 1833 1187 2168 784 CFG_VIN1A_D23_IN vin1a_d23 vin1b_d0 - - -
AH6 vin1a_d3 1588 1289 1993 901 CFG_VIN1A_D3_IN vin1a_d3 - - - -
AH3 vin1a_d4 1687 949 2098 499 CFG_VIN1A_D4_IN vin1a_d4 - - - -
AH5 vin1a_d5 1616 1257 2038 844 CFG_VIN1A_D5_IN vin1a_d5 - - - -
AG6 vin1a_d6 1582 1265 2002 863 CFG_VIN1A_D6_IN vin1a_d6 - - - -
AH4 vin1a_d7 1659 1255 2063 873 CFG_VIN1A_D7_IN vin1a_d7 - - - -
AG4 vin1a_d8 1681 1205 2088 759 CFG_VIN1A_D8_IN vin1a_d8 vin1b_d7 - - -
AG2 vin1a_d9 1778 1168 2152 701 CFG_VIN1A_D9_IN vin1a_d9 vin1b_d6 - - -
AD9 vin1a_de0 1468 1290 1926 728 CFG_VIN1A_DE0_IN vin1a_de0 vin1b_hsync1 - - -
AF9 vin1a_fld0 1633 1425 2043 937 CFG_VIN1A_FLD0_IN vin1a_fld0 vin1b_vsync1 - - -
AE9 vin1a_hsync0 1561 1424 1978 909 CFG_VIN1A_HSYNC0_IN vin1a_hsync0 vin1b_fld1 - - -
AF8 vin1a_vsync0 1470 1369 1926 987 CFG_VIN1A_VSYNC0_IN vin1a_vsync0 vin1b_de1 - - -
AH7 vin1b_clk1 69 150 242 0 CFG_VIN1B_CLK1_IN vin1b_clk1 - - - -
E1 vin2a_clk0 0 0 0 0 CFG_VIN2A_CLK0_IN vin2a_clk0 - - - -
F2 vin2a_d0 1597 561 2009 147 CFG_VIN2A_D0_IN vin2a_d0 - - - -
F3 vin2a_d1 1598 801 2015 561 CFG_VIN2A_D1_IN vin2a_d1 - - - -
D3 vin2a_d10 1576 655 2021 377 CFG_VIN2A_D10_IN vin2a_d10 - - - -
F6 vin2a_d11 1488 340 1940 19 CFG_VIN2A_D11_IN vin2a_d11 - - - -
D5 vin2a_d12 1399 612 1895 181 CFG_VIN2A_D12_IN vin2a_d12 - - - -
C2 vin2a_d13 1595 439 2063 15 CFG_VIN2A_D13_IN vin2a_d13 - - - -
C3 vin2a_d14 1480 243 1709 0 CFG_VIN2A_D14_IN vin2a_d14 - - - -
C4 vin2a_d15 1415 755 1899 369 CFG_VIN2A_D15_IN vin2a_d15 - - - -
B2 vin2a_d16 1341 653 1821 317 CFG_VIN2A_D16_IN vin2a_d16 - vin2b_d7 - -
D6 vin2a_d17 1396 724 1880 349 CFG_VIN2A_D17_IN vin2a_d17 - vin2b_d6 - -
C5 vin2a_d18 1582 364 1963 0 CFG_VIN2A_D18_IN vin2a_d18 - vin2b_d5 - -
A3 vin2a_d19 1308 289 1681 0 CFG_VIN2A_D19_IN vin2a_d19 - vin2b_d4 - -
D1 vin2a_d2 1600 323 2021 0 CFG_VIN2A_D2_IN vin2a_d2 - - - -
B3 vin2a_d20 1307 586 1772 299 CFG_VIN2A_D20_IN vin2a_d20 - vin2b_d3 - -
B4 vin2a_d21 1301 640 1787 282 CFG_VIN2A_D21_IN vin2a_d21 - vin2b_d2 - -
B5 vin2a_d22 1316 534 1789 223 CFG_VIN2A_D22_IN vin2a_d22 - vin2b_d1 - -
A4 vin2a_d23 1311 613 1788 286 CFG_VIN2A_D23_IN vin2a_d23 - vin2b_d0 - -
E2 vin2a_d3 1765 720 2142 492 CFG_VIN2A_D3_IN vin2a_d3 - - - -
D2 vin2a_d4 1680 282 2071 0 CFG_VIN2A_D4_IN vin2a_d4 - - - -
F4 vin2a_d5 1791 696 2155 461 CFG_VIN2A_D5_IN vin2a_d5 - - - -
C1 vin2a_d6 1538 175 1849 0 CFG_VIN2A_D6_IN vin2a_d6 - - - -
E4 vin2a_d7 1546 451 1977 192 CFG_VIN2A_D7_IN vin2a_d7 - - - -
F5 vin2a_d8 1522 650 1966 391 CFG_VIN2A_D8_IN vin2a_d8 - - - -
E6 vin2a_d9 1546 578 1996 270 CFG_VIN2A_D9_IN vin2a_d9 - - - -
G2 vin2a_de0 1548 623 2036 213 CFG_VIN2A_DE0_IN vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 -
H7 vin2a_fld0 1771 815 2162 566 CFG_VIN2A_FLD0_IN vin2a_fld0 - vin2b_clk1 - -
G1 vin2a_hsync0 1703 587 2071 225 CFG_VIN2A_HSYNC0_IN vin2a_hsync0 - - vin2b_hsync1 -
G6 vin2a_vsync0 1486 464 1895 53 CFG_VIN2A_VSYNC0_IN vin2a_vsync0 - - vin2b_vsync1 -

Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-8Manual Functions Mapping for VIP1 2B for a definition of the Manual modes.

Table 7-8 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-8 Manual Functions Mapping for VIP1 2B

BALL BALL NAME VIP1_2B_MANUAL1 VIP1_2B_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 2 3 4
AC5 gpio6_10 1830 911 2136 593 CFG_GPIO6_10_IN - - vin2b_hsync1
AB4 gpio6_11 1797 1159 2088 926 CFG_GPIO6_11_IN - - vin2b_vsync1
AD4 mmc3_clk (1) (1) (1) (1) CFG_MMC3_CLK_IN - - vin2b_d7
AC4 mmc3_cmd 1769 980 2092 650 CFG_MMC3_CMD_IN - - vin2b_d6
AC7 mmc3_dat0 1678 984 2027 691 CFG_MMC3_DAT0_IN - - vin2b_d5
AC6 mmc3_dat1 1664 883 2031 491 CFG_MMC3_DAT1_IN - - vin2b_d4
AC9 mmc3_dat2 1672 439 2065 0 CFG_MMC3_DAT2_IN - - vin2b_d3
AC3 mmc3_dat3 1762 1078 2089 799 CFG_MMC3_DAT3_IN - - vin2b_d2
AC8 mmc3_dat4 1766 583 2125 135 CFG_MMC3_DAT4_IN - - vin2b_d1
AD6 mmc3_dat5 1777 577 2072 362 CFG_MMC3_DAT5_IN - - vin2b_d0
AB8 mmc3_dat6 1675 808 2035 431 CFG_MMC3_DAT6_IN - - vin2b_de1
AB5 mmc3_dat7 0 0 0 0 CFG_MMC3_DAT7_IN - - vin2b_clk1
B2 vin2a_d16 1181 0 1424 0 CFG_VIN2A_D16_IN vin2b_d7 - -
D6 vin2a_d17 1317 0 1545 0 CFG_VIN2A_D17_IN vin2b_d6 - -
C5 vin2a_d18 1132 0 1240 0 CFG_VIN2A_D18_IN vin2b_d5 - -
A3 vin2a_d19 749 0 919 0 CFG_VIN2A_D19_IN vin2b_d4 - -
B3 vin2a_d20 1078 0 1320 0 CFG_VIN2A_D20_IN vin2b_d3 - -
B4 vin2a_d21 1119 0 1357 0 CFG_VIN2A_D21_IN vin2b_d2 - -
B5 vin2a_d22 1089 0 1306 0 CFG_VIN2A_D22_IN vin2b_d1 - -
A4 vin2a_d23 1118 0 1362 0 CFG_VIN2A_D23_IN vin2b_d0 - -
G2 vin2a_de0 1371 420 1813 86 CFG_VIN2A_DE0_IN vin2b_fld1 vin2b_de1 -
H7 vin2a_fld0 0 0 0 0 CFG_VIN2A_FLD0_IN vin2b_clk1 - -
G1 vin2a_hsync0 1605 0 1674 0 CFG_VIN2A_HSYNC0_IN - vin2b_hsync1 -
G6 vin2a_vsync0 1231 0 1300 0 CFG_VIN2A_VSYNC0_IN - vin2b_vsync1 -
  1. The CFG_MMC3_CLK_IN register should remain at its Default value, which is programmed automatically by hardware during the recalibration process.

Manual IO Timings Modes must be used to ensure some IO timings for VIP2. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-9Manual Functions Mapping for VIP2 for a definition of the Manual modes.

Table 7-9 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-9 Manual Functions Mapping for VIP2

BALL BALL NAME VIP2_MANUAL 1 VIP2_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 2 3 4 5 6
R6 gpmc_a0 2216 947 2519 702 CFG_GPMC_A0_IN vin3a_d16 - vin4a_d0 - -
T9 gpmc_a1 2078 1022 2384 778 CFG_GPMC_A1_IN vin3a_d17 - vin4a_d1 - -
N9 gpmc_a10 2108 823 2435 411 CFG_GPMC_A10_IN vin3a_de0 - - - -
P9 gpmc_a11 2068 977 2379 755 CFG_GPMC_A11_IN vin3a_fld0 - vin4a_fld0 - -
K7 gpmc_a19 1740 123 1743 0 CFG_GPMC_A19_IN - - vin4a_d12 - vin3b_d0
T6 gpmc_a2 2280 1298 2499 1127 CFG_GPMC_A2_IN vin3a_d18 - vin4a_d2 - -
M7 gpmc_a20 1628 30 1529 0 CFG_GPMC_A20_IN - - vin4a_d13 - vin3b_d1
J5 gpmc_a21 1687 217 1779 0 CFG_GPMC_A21_IN - - vin4a_d14 - vin3b_d2
K6 gpmc_a22 1595 151 1620 0 CFG_GPMC_A22_IN - - vin4a_d15 - vin3b_d3
J7 gpmc_a23 1366 0 1363 0 CFG_GPMC_A23_IN - - vin4a_fld0 - vin3b_d4
J4 gpmc_a24 1554 343 1765 0 CFG_GPMC_A24_IN - - - - vin3b_d5
J6 gpmc_a25 1652 268 1808 0 CFG_GPMC_A25_IN - - - - vin3b_d6
H4 gpmc_a26 1546 281 1669 0 CFG_GPMC_A26_IN - - - - vin3b_d7
H5 gpmc_a27 1534 198 1611 0 CFG_GPMC_A27_IN - - - - vin3b_hsync1
T7 gpmc_a3 2246 1318 2455 1181 CFG_GPMC_A3_IN vin3a_d19 - vin4a_d3 - -
P6 gpmc_a4 2266 1216 2486 1039 CFG_GPMC_A4_IN vin3a_d20 - vin4a_d4 - -
R9 gpmc_a5 2185 1122 2456 938 CFG_GPMC_A5_IN vin3a_d21 - vin4a_d5 - -
R5 gpmc_a6 2206 782 2463 573 CFG_GPMC_A6_IN vin3a_d22 - vin4a_d6 - -
P5 gpmc_a7 2369 1025 2608 783 CFG_GPMC_A7_IN vin3a_d23 - vin4a_d7 - -
N7 gpmc_a8 2154 978 2430 656 CFG_GPMC_A8_IN vin3a_hsync0 - - - -
R4 gpmc_a9 2185 1152 2465 850 CFG_GPMC_A9_IN vin3a_vsync0 - - - -
M6 gpmc_ad0 1908 620 2316 301 CFG_GPMC_AD0_IN vin3a_d0 - - - -
M2 gpmc_ad1 2117 382 2440 70 CFG_GPMC_AD1_IN vin3a_d1 - - - -
J1 gpmc_ad10 1968 686 2324 406 CFG_GPMC_AD10_IN vin3a_d10 - - - -
J2 gpmc_ad11 1853 689 2278 352 CFG_GPMC_AD11_IN vin3a_d11 - - - -
H1 gpmc_ad12 1910 497 2297 160 CFG_GPMC_AD12_IN vin3a_d12 - - - -
J3 gpmc_ad13 1869 436 2278 108 CFG_GPMC_AD13_IN vin3a_d13 - - - -
H2 gpmc_ad14 1895 147 2035 0 CFG_GPMC_AD14_IN vin3a_d14 - - - -
H3 gpmc_ad15 1917 655 2279 378 CFG_GPMC_AD15_IN vin3a_d15 - - - -
L5 gpmc_ad2 2097 666 2404 446 CFG_GPMC_AD2_IN vin3a_d2 - - - -
M1 gpmc_ad3 1954 581 2343 212 CFG_GPMC_AD3_IN vin3a_d3 - - - -
L6 gpmc_ad4 2034 610 2355 322 CFG_GPMC_AD4_IN vin3a_d4 - - - -
L4 gpmc_ad5 1965 484 2337 192 CFG_GPMC_AD5_IN vin3a_d5 - - - -
L3 gpmc_ad6 1861 635 2270 314 CFG_GPMC_AD6_IN vin3a_d6 - - - -
L2 gpmc_ad7 2004 507 2339 259 CFG_GPMC_AD7_IN vin3a_d7 - - - -
L1 gpmc_ad8 1945 853 2308 577 CFG_GPMC_AD8_IN vin3a_d8 - - - -
K2 gpmc_ad9 1914 539 2334 166 CFG_GPMC_AD9_IN vin3a_d9 - - - -
N6 gpmc_ben0 1806 0 1722 0 CFG_GPMC_BEN0_IN - - - - vin3b_de1
M4 gpmc_ben1 1879 20 1840 0 CFG_GPMC_BEN1_IN - - vin3b_clk1 - vin3b_fld1
P7 gpmc_clk 0 0 0 0 CFG_GPMC_CLK_IN - - vin4a_hsync0 vin4a_de0 vin3b_clk1
H6 gpmc_cs1 1505 41 1388 0 CFG_GPMC_CS1_IN - - vin4a_de0 - vin3b_vsync1
P1 gpmc_cs3 0 0 0 0 CFG_GPMC_CS3_IN vin3a_clk0 - - - -
AF1 vin1a_d16 1803 1679 2244 1202 CFG_VIN1A_D16_IN - - - - vin3a_d0
AE3 vin1a_d17 1871 1654 2321 1116 CFG_VIN1A_D17_IN - - - - vin3a_d1
AE5 vin1a_d18 1875 1742 2280 1288 CFG_VIN1A_D18_IN - - - - vin3a_d2
AE1 vin1a_d19 1844 1759 2282 1281 CFG_VIN1A_D19_IN - - - - vin3a_d3
AE2 vin1a_d20 1845 1624 2284 1090 CFG_VIN1A_D20_IN - - - - vin3a_d4
AE6 vin1a_d21 1906 1520 2324 1000 CFG_VIN1A_D21_IN - - - - vin3a_d5
AD2 vin1a_d22 1807 1437 2278 915 CFG_VIN1A_D22_IN - - - - vin3a_d6
AD3 vin1a_d23 1996 997 2423 398 CFG_VIN1A_D23_IN - - - - vin3a_d7
AH7 vin1b_clk1 0 0 0 0 CFG_VIN1B_CLK1_IN - - - - vin3a_clk0
B2 vin2a_d16 1329 528 1779 0 CFG_VIN2A_D16_IN - - - - vin3a_d8
D6 vin2a_d17 1270 677 1844 0 CFG_VIN2A_D17_IN - - - - vin3a_d9
C5 vin2a_d18 1494 411 1767 0 CFG_VIN2A_D18_IN - - - - vin3a_d10
A3 vin2a_d19 1225 154 1254 0 CFG_VIN2A_D19_IN - - - - vin3a_d11
B3 vin2a_d20 1212 450 1597 0 CFG_VIN2A_D20_IN - - - vin3a_de0 vin3a_d12
B4 vin2a_d21 1232 494 1662 0 CFG_VIN2A_D21_IN - - - vin3a_fld0 vin3a_d13
B5 vin2a_d22 1203 503 1641 0 CFG_VIN2A_D22_IN - - - vin3a_hsync0 vin3a_d14
A4 vin2a_d23 1214 599 1748 0 CFG_VIN2A_D23_IN - - - vin3a_vsync0 vin3a_d15
D11 vout1_clk 2047 735 2391 637 CFG_VOUT1_CLK_IN - vin4a_fld0 vin3a_fld0 - -
F11 vout1_d0 2135 987 2403 965 CFG_VOUT1_D0_IN - vin4a_d16 vin3a_d16 - -
G10 vout1_d1 2048 955 2368 880 CFG_VOUT1_D1_IN - vin4a_d17 vin3a_d17 - -
D7 vout1_d10 1970 855 2347 724 CFG_VOUT1_D10_IN - vin4a_d10 vin3a_d10 - -
D8 vout1_d11 2111 893 2389 861 CFG_VOUT1_D11_IN - vin4a_d11 vin3a_d11 - -
A5 vout1_d12 2018 841 2356 748 CFG_VOUT1_D12_IN - vin4a_d12 vin3a_d12 - -
C6 vout1_d13 2073 805 2382 731 CFG_VOUT1_D13_IN - vin4a_d13 vin3a_d13 - -
C8 vout1_d14 2112 770 2401 703 CFG_VOUT1_D14_IN - vin4a_d14 vin3a_d14 - -
C7 vout1_d15 2132 831 2434 771 CFG_VOUT1_D15_IN - vin4a_d15 vin3a_d15 - -
B7 vout1_d16 1996 632 2338 536 CFG_VOUT1_D16_IN - vin4a_d0 vin3a_d0 - -
B8 vout1_d17 2190 790 2442 775 CFG_VOUT1_D17_IN - vin4a_d1 vin3a_d1 - -
A7 vout1_d18 2100 604 2385 565 CFG_VOUT1_D18_IN - vin4a_d2 vin3a_d2 - -
A8 vout1_d19 2108 286 2424 168 CFG_VOUT1_D19_IN - vin4a_d3 vin3a_d3 - -
F10 vout1_d2 1979 1020 2335 909 CFG_VOUT1_D2_IN - vin4a_d18 vin3a_d18 - -
C9 vout1_d20 2031 967 2362 881 CFG_VOUT1_D20_IN - vin4a_d4 vin3a_d4 - -
A9 vout1_d21 2039 450 2350 384 CFG_VOUT1_D21_IN - vin4a_d5 vin3a_d5 - -
B9 vout1_d22 2037 583 2369 497 CFG_VOUT1_D22_IN - vin4a_d6 vin3a_d6 - -
A10 vout1_d23 1768 740 2246 508 CFG_VOUT1_D23_IN - vin4a_d7 vin3a_d7 - -
G11 vout1_d3 2099 881 2382 844 CFG_VOUT1_D3_IN - vin4a_d19 vin3a_d19 - -
E9 vout1_d4 2120 786 2387 756 CFG_VOUT1_D4_IN - vin4a_d20 vin3a_d20 - -
F9 vout1_d5 1965 857 2299 769 CFG_VOUT1_D5_IN - vin4a_d21 vin3a_d21 - -
F8 vout1_d6 2139 680 2366 699 CFG_VOUT1_D6_IN - vin4a_d22 vin3a_d22 - -
E7 vout1_d7 2122 912 2360 920 CFG_VOUT1_D7_IN - vin4a_d23 vin3a_d23 - -
E8 vout1_d8 2073 906 2372 853 CFG_VOUT1_D8_IN - vin4a_d8 vin3a_d8 - -
D9 vout1_d9 2097 934 2386 879 CFG_VOUT1_D9_IN - vin4a_d9 vin3a_d9 - -
B10 vout1_de 2021 527 2366 428 CFG_VOUT1_DE_IN - vin4a_de0 vin3a_de0 - -
B11 vout1_fld 0 0 0 0 CFG_VOUT1_FLD_IN - vin4a_clk0 vin3a_clk0 - -
C11 vout1_hsync 1775 486 2272 164 CFG_VOUT1_HSYNC_IN - vin4a_hsync0 vin3a_hsync0 - -
E11 vout1_vsync 1917 314 2301 0 CFG_VOUT1_VSYNC_IN - vin4a_vsync0 vin3a_vsync0 - -

Manual IO Timings Modes must be used to ensure some IO timings for VIP2. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-10Manual Functions Mapping for VIP2 4A for a definition of the Manual modes.

Table 7-10 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-10 Manual Functions Mapping for VIP2 4A

BALL BALL NAME VIP2_4A_MANUAL1 VIP2_4A_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 3 4 5
R6 gpmc_a0 1801 521 2268 0 CFG_GPMC_A0_IN - vin4a_d0 -
T9 gpmc_a1 1668 488 2135 0 CFG_GPMC_A1_IN - vin4a_d1 -
P9 gpmc_a11 1694 308 2026 0 CFG_GPMC_A11_IN - vin4a_fld0 -
P4 gpmc_a12 0 0 0 0 CFG_GPMC_A12_IN - vin4a_clk0 -
R3 gpmc_a13 1529 570 2029 38 CFG_GPMC_A13_IN - vin4a_hsync0 -
T2 gpmc_a14 1747 753 2266 261 CFG_GPMC_A14_IN - vin4a_vsync0 -
U2 gpmc_a15 1536 336 1882 0 CFG_GPMC_A15_IN - vin4a_d8 -
U1 gpmc_a16 1662 293 1936 0 CFG_GPMC_A16_IN - vin4a_d9 -
P3 gpmc_a17 1637 247 1851 0 CFG_GPMC_A17_IN - vin4a_d10 -
R2 gpmc_a18 1454 0 1369 0 CFG_GPMC_A18_IN - vin4a_d11 -
K7 gpmc_a19 1577 205 1634 0 CFG_GPMC_A19_IN - vin4a_d12 -
T6 gpmc_a2 1891 747 2369 238 CFG_GPMC_A2_IN - vin4a_d2 -
M7 gpmc_a20 1398 220 1450 0 CFG_GPMC_A20_IN - vin4a_d13 -
J5 gpmc_a21 1521 329 1691 0 CFG_GPMC_A21_IN - vin4a_d14 -
K6 gpmc_a22 1383 273 1488 0 CFG_GPMC_A22_IN - vin4a_d15 -
J7 gpmc_a23 1163 0 1147 0 CFG_GPMC_A23_IN - vin4a_fld0 -
T7 gpmc_a3 1820 786 2325 271 CFG_GPMC_A3_IN - vin4a_d3 -
P6 gpmc_a4 1865 662 2359 126 CFG_GPMC_A4_IN - vin4a_d4 -
R9 gpmc_a5 1722 629 2260 53 CFG_GPMC_A5_IN - vin4a_d5 -
R5 gpmc_a6 1755 279 1990 0 CFG_GPMC_A6_IN - vin4a_d6 -
P5 gpmc_a7 1979 506 2410 0 CFG_GPMC_A7_IN - vin4a_d7 -
N1 gpmc_advn_ale 1793 267 2045 0 CFG_GPMC_ADVN_ALE_IN - vin4a_vsync0 -
P7 gpmc_clk 1738 309 2040 0 CFG_GPMC_CLK_IN - vin4a_hsync0 vin4a_de0
H6 gpmc_cs1 1379 95 1361 0 CFG_GPMC_CS1_IN - vin4a_de0 -
D11 vout1_clk 2090 401 2409 357 CFG_VOUT1_CLK_IN vin4a_fld0 - -
F11 vout1_d0 2139 961 2394 981 CFG_VOUT1_D0_IN vin4a_d16 - -
G10 vout1_d1 1993 878 2347 799 CFG_VOUT1_D1_IN vin4a_d17 - -
D7 vout1_d10 1976 678 2346 583 CFG_VOUT1_D10_IN vin4a_d10 - -
D8 vout1_d11 2135 749 2393 767 CFG_VOUT1_D11_IN vin4a_d11 - -
A5 vout1_d12 2014 696 2351 634 CFG_VOUT1_D12_IN vin4a_d12 - -
C6 vout1_d13 2035 590 2370 531 CFG_VOUT1_D13_IN vin4a_d13 - -
C8 vout1_d14 2108 861 2385 860 CFG_VOUT1_D14_IN vin4a_d14 - -
C7 vout1_d15 2074 682 2423 609 CFG_VOUT1_D15_IN vin4a_d15 - -
B7 vout1_d16 1976 579 2331 500 CFG_VOUT1_D16_IN vin4a_d0 - -
B8 vout1_d17 2203 505 2464 509 CFG_VOUT1_D17_IN vin4a_d1 - -
A7 vout1_d18 2096 412 2394 390 CFG_VOUT1_D18_IN vin4a_d2 - -
A8 vout1_d19 2106 72 2423 21 CFG_VOUT1_D19_IN vin4a_d3 - -
F10 vout1_d2 2023 648 2374 572 CFG_VOUT1_D2_IN vin4a_d18 - -
C9 vout1_d20 2027 767 2370 700 CFG_VOUT1_D20_IN vin4a_d4 - -
A9 vout1_d21 2026 184 2354 128 CFG_VOUT1_D21_IN vin4a_d5 - -
B9 vout1_d22 2061 195 2397 135 CFG_VOUT1_D22_IN vin4a_d6 - -
A10 vout1_d23 1764 607 2251 396 CFG_VOUT1_D23_IN vin4a_d7 - -
G11 vout1_d3 2053 757 2377 707 CFG_VOUT1_D3_IN vin4a_d19 - -
E9 vout1_d4 2119 617 2392 619 CFG_VOUT1_D4_IN vin4a_d20 - -
F9 vout1_d5 1951 712 2305 633 CFG_VOUT1_D5_IN vin4a_d21 - -
F8 vout1_d6 2119 515 2365 543 CFG_VOUT1_D6_IN vin4a_d22 - -
E7 vout1_d7 2119 779 2363 810 CFG_VOUT1_D7_IN vin4a_d23 - -
E8 vout1_d8 2043 807 2357 768 CFG_VOUT1_D8_IN vin4a_d8 - -
D9 vout1_d9 2166 643 2412 671 CFG_VOUT1_D9_IN vin4a_d9 - -
B10 vout1_de 1982 410 2353 314 CFG_VOUT1_DE_IN vin4a_de0 - -
B11 vout1_fld 0 0 0 0 CFG_VOUT1_FLD_IN vin4a_clk0 - -
C11 vout1_hsync 1755 305 2269 4 CFG_VOUT1_HSYNC_IN vin4a_hsync0 - -
E11 vout1_vsync 1924 8 2066 0 CFG_VOUT1_VSYNC_IN vin4a_vsync0 - -

Manual IO Timings Modes must be used to ensure some IO timings for VIP2. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-11Manual Functions Mapping for VIP2 4A IOSET3 for a definition of the Manual modes.

Table 7-11 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-11 Manual Functions Mapping for VIP2 4A IOSET3

BALL BALL NAME VIP2_4A_IOSET3_MANUAL1 VIP2_4A_IOSET3_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 8
E21 gpio6_14 683 0 939 0 CFG_GPIO6_14_IN vin4a_hsync0
F20 gpio6_15 1065 0 1321 0 CFG_GPIO6_15_IN vin4a_vsync0
F21 gpio6_16 858 0 1114 0 CFG_GPIO6_16_IN vin4a_fld0
B14 mcasp1_aclkr 1711 23 1990 0 CFG_MCASP1_ACLKR_IN vin4a_d0
G13 mcasp1_axr2 2131 1054 2423 1073 CFG_MCASP1_AXR2_IN vin4a_d2
J11 mcasp1_axr3 2267 691 2573 696 CFG_MCASP1_AXR3_IN vin4a_d3
E12 mcasp1_axr4 2089 813 2441 773 CFG_MCASP1_AXR4_IN vin4a_d4
F13 mcasp1_axr5 2061 858 2430 799 CFG_MCASP1_AXR5_IN vin4a_d5
C12 mcasp1_axr6 2151 595 2539 480 CFG_MCASP1_AXR6_IN vin4a_d6
D12 mcasp1_axr7 2112 931 2421 932 CFG_MCASP1_AXR7_IN vin4a_d7
J14 mcasp1_fsr 1714 323 2248 44 CFG_MCASP1_FSR_IN vin4a_d1
E15 mcasp2_aclkr 1462 76 1795 0 CFG_MCASP2_ACLKR_IN vin4a_d8
B15 mcasp2_axr0 1578 833 2113 554 CFG_MCASP2_AXR0_IN vin4a_d10
A15 mcasp2_axr1 1785 396 2279 212 CFG_MCASP2_AXR1_IN vin4a_d11
D15 mcasp2_axr4 1765 485 2299 206 CFG_MCASP2_AXR4_IN vin4a_d12
B16 mcasp2_axr5 1644 509 2179 230 CFG_MCASP2_AXR5_IN vin4a_d13
B17 mcasp2_axr6 1098 0 1354 0 CFG_MCASP2_AXR6_IN vin4a_d14
A17 mcasp2_axr7 1242 521 1777 243 CFG_MCASP2_AXR7_IN vin4a_d15
A20 mcasp2_fsr 1328 130 1713 0 CFG_MCASP2_FSR_IN vin4a_d9
C18 mcasp4_aclkx 1033 0 1166 0 CFG_MCASP4_ACLKX_IN vin4a_d16
G16 mcasp4_axr0 2147 358 2529 221 CFG_MCASP4_AXR0_IN vin4a_d18
D17 mcasp4_axr1 2140 676 2482 645 CFG_MCASP4_AXR1_IN vin4a_d19
A21 mcasp4_fsx 2140 339 2554 165 CFG_MCASP4_FSX_IN vin4a_d17
AA3 mcasp5_aclkx 2846 2620 3059 2547 CFG_MCASP5_ACLKX_IN vin4a_d20
AB3 mcasp5_axr0 2880 3301 3040 3417 CFG_MCASP5_AXR0_IN vin4a_d22
AA4 mcasp5_axr1 2851 3586 3042 3593 CFG_MCASP5_AXR1_IN vin4a_d23
AB9 mcasp5_fsx 2847 2856 3031 2890 CFG_MCASP5_FSX_IN vin4a_d21
B26 xref_clk2 0 0 0 0 CFG_XREF_CLK2_IN vin4a_clk0
C23 xref_clk3 927 0 1183 0 CFG_XREF_CLK3_IN vin4a_de0

Manual IO Timings Modes must be used to ensure some IO timings for VIP2. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-12Manual Functions Mapping for VIP2 4B for a definition of the Manual modes.

Table 7-12 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-12 Manual Functions Mapping for VIP2 4B

BALL BALL NAME VIP2_4B_MANUAL1 VIP2_4B_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 5 6
R6 gpmc_a0 1861 901 2102 660 CFG_GPMC_A0_IN - vin4b_d0
T9 gpmc_a1 1652 891 1955 583 CFG_GPMC_A1_IN - vin4b_d1
N9 gpmc_a10 0 0 0 0 CFG_GPMC_A10_IN - vin4b_clk1
P9 gpmc_a11 1783 1178 1975 1021 CFG_GPMC_A11_IN - vin4b_de1
P4 gpmc_a12 1903 853 2076 664 CFG_GPMC_A12_IN - vin4b_fld1
T6 gpmc_a2 1888 1212 2065 994 CFG_GPMC_A2_IN - vin4b_d2
T7 gpmc_a3 1839 1274 2025 1075 CFG_GPMC_A3_IN - vin4b_d3
P6 gpmc_a4 1868 1113 2058 869 CFG_GPMC_A4_IN - vin4b_d4
R9 gpmc_a5 1757 1079 2028 802 CFG_GPMC_A5_IN - vin4b_d5
R5 gpmc_a6 1800 670 2032 421 CFG_GPMC_A6_IN - vin4b_d6
P5 gpmc_a7 1967 898 2179 597 CFG_GPMC_A7_IN - vin4b_d7
N7 gpmc_a8 1731 959 1993 559 CFG_GPMC_A8_IN - vin4b_hsync1
R4 gpmc_a9 1766 1150 2022 834 CFG_GPMC_A9_IN - vin4b_vsync1
U4 mdio_d 1602 506 1931 283 CFG_MDIO_D_IN vin4b_d0 -
V1 mdio_mclk 0 0 0 0 CFG_MDIO_MCLK_IN vin4b_clk1 -
U5 rgmii0_rxc 1678 887 1987 663 CFG_RGMII0_RXC_IN vin4b_d5 -
V5 rgmii0_rxctl 1595 932 1903 748 CFG_RGMII0_RXCTL_IN vin4b_d6 -
W2 rgmii0_rxd0 1707 464 2010 160 CFG_RGMII0_RXD0_IN vin4b_fld1 -
V4 rgmii0_rxd3 1662 1146 1943 996 CFG_RGMII0_RXD3_IN vin4b_d7 -
W9 rgmii0_txc 1639 1195 1970 1006 CFG_RGMII0_TXC_IN vin4b_d3 -
V9 rgmii0_txctl 1695 1226 1952 1113 CFG_RGMII0_TXCTL_IN vin4b_d4 -
V6 rgmii0_txd1 1693 1118 1951 1003 CFG_RGMII0_TXD1_IN vin4b_vsync1 -
U7 rgmii0_txd2 1522 1004 1895 685 CFG_RGMII0_TXD2_IN vin4b_hsync1 -
V7 rgmii0_txd3 1777 957 2018 787 CFG_RGMII0_TXD3_IN vin4b_de1 -
V2 uart3_rxd 1537 236 1762 0 CFG_UART3_RXD_IN vin4b_d1 -
Y1 uart3_txd 1575 645 1933 276 CFG_UART3_TXD_IN vin4b_d2 -

Manual IO Timings Modes must be used to ensure some IO timings for VIP2. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-13Manual Functions Mapping for VIP2 3B IOSET2 for a definition of the Manual modes.

Table 7-13 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-13 Manual Functions Mapping for VIP2 3B IOSET2

BALL BALL NAME VIP2_3B_IOSET2_MANUAL1 VIP2_3B_IOSET2_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 4 6
K7 gpmc_a19 1505 1172 1854 799 CFG_GPMC_A19_IN - vin3b_d0
M7 gpmc_a20 1394 1074 1723 716 CFG_GPMC_A20_IN - vin3b_d1
J5 gpmc_a21 1452 1266 1789 900 CFG_GPMC_A21_IN - vin3b_d2
K6 gpmc_a22 1360 1200 1684 847 CFG_GPMC_A22_IN - vin3b_d3
J7 gpmc_a23 1446 735 1831 443 CFG_GPMC_A23_IN - vin3b_d4
J4 gpmc_a24 1329 1360 1686 970 CFG_GPMC_A24_IN - vin3b_d5
J6 gpmc_a25 1417 1318 1757 962 CFG_GPMC_A25_IN - vin3b_d6
H4 gpmc_a26 1321 1298 1680 880 CFG_GPMC_A26_IN - vin3b_d7
H5 gpmc_a27 1309 1215 1669 834 CFG_GPMC_A27_IN - vin3b_hsync1
N6 gpmc_ben0 1677 944 1994 638 CFG_GPMC_BEN0_IN - vin3b_de1
M4 gpmc_ben1 0 0 0 0 CFG_GPMC_BEN1_IN vin3b_clk1 vin3b_fld1
H6 gpmc_cs1 1280 1058 1620 664 CFG_GPMC_CS1_IN - vin3b_vsync1

Manual IO Timings Modes must be used to ensure some IO timings for VIP3. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-14Manual Functions Mapping for VIP3 for a definition of the Manual modes.

Table 7-14 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-14 Manual Functions Mapping for VIP3

BALL BALL NAME VIP3_MANUAL1 VIP3_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 7 9
AC5 gpio6_10 774 2462 765 2551 CFG_GPIO6_10_IN - vin5a_clk0
AB4 gpio6_11 2453 3000 2863 2719 CFG_GPIO6_11_IN - vin5a_de0
C14 mcasp1_aclkx 1400 154 1698 0 CFG_MCASP1_ACLKX_IN vin6a_fld0 -
G12 mcasp1_axr0 2055 612 2459 381 CFG_MCASP1_AXR0_IN vin6a_vsync0 -
F12 mcasp1_axr1 1623 338 2098 0 CFG_MCASP1_AXR1_IN vin6a_hsync0 -
B13 mcasp1_axr10 1625 92 1681 0 CFG_MCASP1_AXR10_IN vin6a_d13 -
A12 mcasp1_axr11 1509 714 2048 317 CFG_MCASP1_AXR11_IN vin6a_d12 -
E14 mcasp1_axr12 1189 619 1729 222 CFG_MCASP1_AXR12_IN vin6a_d11 -
A13 mcasp1_axr13 1546 265 1954 0 CFG_MCASP1_AXR13_IN vin6a_d10 -
G14 mcasp1_axr14 1305 0 1448 0 CFG_MCASP1_AXR14_IN vin6a_d9 -
F14 mcasp1_axr15 1342 313 1798 0 CFG_MCASP1_AXR15_IN vin6a_d8 -
B12 mcasp1_axr8 1833 466 2264 0 CFG_MCASP1_AXR8_IN vin6a_d15 -
A11 mcasp1_axr9 1555 777 2029 352 CFG_MCASP1_AXR9_IN vin6a_d14 -
D14 mcasp1_fsx 1549 281 1972 0 CFG_MCASP1_FSX_IN vin6a_de0 -
A19 mcasp2_aclkx 1063 0 1206 0 CFG_MCASP2_ACLKX_IN vin6a_d7 -
C15 mcasp2_axr2 1134 0 1277 0 CFG_MCASP2_AXR2_IN vin6a_d5 -
A16 mcasp2_axr3 1348 487 1888 90 CFG_MCASP2_AXR3_IN vin6a_d4 -
A18 mcasp2_fsx 1030 250 1424 0 CFG_MCASP2_FSX_IN vin6a_d6 -
B18 mcasp3_aclkx 0 0 0 0 CFG_MCASP3_ACLKX_IN vin6a_d3 -
B19 mcasp3_axr0 888 485 1428 88 CFG_MCASP3_AXR0_IN vin6a_d1 -
C17 mcasp3_axr1 861 582 1331 254 CFG_MCASP3_AXR1_IN vin6a_d0 vin5a_fld0
F15 mcasp3_fsx 1093 451 1633 54 CFG_MCASP3_FSX_IN vin6a_d2 -
C18 mcasp4_aclkx 557 0 541 0 CFG_MCASP4_ACLKX_IN - vin5a_d15
G16 mcasp4_axr0 1027 989 1441 644 CFG_MCASP4_AXR0_IN - vin5a_d13
D17 mcasp4_axr1 1140 1038 1601 740 CFG_MCASP4_AXR1_IN - vin5a_d12
A21 mcasp4_fsx 1140 885 700 1377 CFG_MCASP4_FSX_IN - vin5a_d14
AA3 mcasp5_aclkx 1633 3030 1658 2999 CFG_MCASP5_ACLKX_IN - vin5a_d11
AB3 mcasp5_axr0 2392 3028 2816 2711 CFG_MCASP5_AXR0_IN - vin5a_d9
AA4 mcasp5_axr1 2435 3026 2856 2723 CFG_MCASP5_AXR1_IN - vin5a_d8
AB9 mcasp5_fsx 2285 2660 2713 2288 CFG_MCASP5_FSX_IN - vin5a_d10
AD4 mmc3_clk 2501 2822 2915 2475 CFG_MMC3_CLK_IN - vin5a_d7
AC4 mmc3_cmd 2423 2826 2832 2485 CFG_MMC3_CMD_IN - vin5a_d6
AC7 mmc3_dat0 2336 2820 2743 2526 CFG_MMC3_DAT0_IN - vin5a_d5
AC6 mmc3_dat1 2332 2710 2749 2346 CFG_MMC3_DAT1_IN - vin5a_d4
AC9 mmc3_dat2 1732 3048 1811 3012 CFG_MMC3_DAT2_IN - vin5a_d3
AC3 mmc3_dat3 2459 2969 2872 2683 CFG_MMC3_DAT3_IN - vin5a_d2
AC8 mmc3_dat4 2436 2662 2836 2271 CFG_MMC3_DAT4_IN - vin5a_d1
AD6 mmc3_dat5 2450 2431 1771 3271 CFG_MMC3_DAT5_IN - vin5a_d0
AB8 mmc3_dat6 2332 2640 2752 2255 CFG_MMC3_DAT6_IN - vin5a_hsync0
AB5 mmc3_dat7 1799 2927 1881 2844 CFG_MMC3_DAT7_IN - vin5a_vsync0
D18 xref_clk0 681 0 824 0 CFG_XREF_CLK0_IN vin6a_d0 -
E17 xref_clk1 21 0 0 0 CFG_XREF_CLK1_IN vin6a_clk0 -