SPRS950F December   2015  – May 2019 DRA745 , DRA746 , DRA750 , DRA756

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  External Memory Interface (EMIF)
      5. 4.4.5  General-Purpose Memory Controller (GPMC)
      6. 4.4.6  Timers
      7. 4.4.7  Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8  HDQ / 1-Wire Interface (HDQ1W)
      9. 4.4.9  Universal Asynchronous Receiver Transmitter (UART)
      10. 4.4.10 Multichannel Serial Peripheral Interface (McSPI)
      11. 4.4.11 Quad Serial Peripheral Interface (QSPI)
      12. 4.4.12 Multichannel Audio Serial Port (McASP)
      13. 4.4.13 Universal Serial Bus (USB)
      14. 4.4.14 SATA
      15. 4.4.15 Peripheral Component Interconnect Express (PCIe)
      16. 4.4.16 Controller Area Network Interface (DCAN)
      17. 4.4.17 Ethernet Interface (GMAC_SW)
      18. 4.4.18 Media Local Bus (MLB) Interface
      19. 4.4.19 eMMC/SD/SDIO
      20. 4.4.20 General-Purpose Interface (GPIO)
      21. 4.4.21 Keyboard controller (KBD)
      22. 4.4.22 Pulse Width Modulation (PWM) Interface
      23. 4.4.23 Audio Tracking Logic (ATL)
      24. 4.4.24 Test Interfaces
      25. 4.4.25 System and Miscellaneous
        1. 4.4.25.1 Sysboot
        2. 4.4.25.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.25.3 Real Time Clock (RTC) Interface
        4. 4.4.25.4 System Direct Memory Access (SDMA)
        5. 4.4.25.5 Interrupt Controllers (INTC)
        6. 4.4.25.6 Observability
      26. 4.4.26 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  ILVDS18 Buffers DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 PCIEPHY DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 RC On-die Oscillator Clock
    3. 6.3 DPLLs, DLLs Specifications
      1. 6.3.1 DPLL Characteristics
      2. 6.3.2 DLL Characteristics
      3. 6.3.3 DPLL and DLL Noise Isolation
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem – Video Output Ports
    8. 7.8  Display Subsystem – High-Definition Multimedia Interface (HDMI)
    9. 7.9  External Memory Interface (EMIF)
    10. 7.10 General-Purpose Memory Controller (GPMC)
      1. 7.10.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11 Timers
    12. 7.12 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-34 Timing Requirements for I2C Input Timings
      2. Table 7-35 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-36 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    13. 7.13 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.13.1 HDQ / 1-Wire — HDQ Mode
      2. 7.13.2 HDQ/1-Wire—1-Wire Mode
    14. 7.14 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-41 Timing Requirements for UART
      2. Table 7-42 Switching Characteristics Over Recommended Operating Conditions for UART
    15. 7.15 Multichannel Serial Peripheral Interface (McSPI)
    16. 7.16 Quad Serial Peripheral Interface (QSPI)
    17. 7.17 Multichannel Audio Serial Port (McASP)
      1. Table 7-49 Timing Requirements for McASP1
      2. Table 7-50 Timing Requirements for McASP2
      3. Table 7-51 Timing Requirements for McASP3/4/5/6/7/8
      4. Table 7-52 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-53 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-54 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
    18. 7.18 Universal Serial Bus (USB)
      1. 7.18.1 USB1 DRD PHY
      2. 7.18.2 USB2 PHY
      3. 7.18.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
    19. 7.19 Serial Advanced Technology Attachment (SATA)
    20. 7.20 Peripheral Component Interconnect Express (PCIe)
    21. 7.21 Controller Area Network Interface (DCAN)
      1. Table 7-69 Timing Requirements for DCANx Receive
      2. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    22. 7.22 Ethernet Interface (GMAC_SW)
      1. 7.22.1 GMAC MII Timings
        1. Table 7-71 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-72 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-73 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-74 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.22.2 GMAC MDIO Interface Timings
      3. 7.22.3 GMAC RMII Timings
        1. Table 7-79 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-80 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-81 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-82 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.22.4 GMAC RGMII Timings
        1. Table 7-86 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-87 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-88 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-89 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    23. 7.23 Media Local Bus (MLB) interface
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1—SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 — eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.24.3 MMC3 and MMC4—SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 Audio Tracking Logic (ATL)
      1. 7.26.1 ATL Electrical Data/Timing
        1. Table 7-145 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
          1. Table 7-146 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-147 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-148 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-149 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Introduction
      1. 8.1.1 Initial Requirements and Guidelines
    2. 8.2 Power Optimizations
      1. 8.2.1 Step 1: PCB Stack-up
      2. 8.2.2 Step 2: Physical Placement
      3. 8.2.3 Step 3: Static Analysis
        1. 8.2.3.1 PDN Resistance and IR Drop
      4. 8.2.4 Step 4: Frequency Analysis
      5. 8.2.5 System ESD Generic Guidelines
        1. 8.2.5.1 System ESD Generic PCB Guideline
        2. 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 8.2.6 EMI / EMC Issues Prevention
        1. 8.2.6.1 Signal Bandwidth
        2. 8.2.6.2 Signal Routing
          1. 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 8.2.6.3 Ground Guidelines
          1. 8.2.6.3.1 PCB Outer Layers
          2. 8.2.6.3.2 Metallic Frames
          3. 8.2.6.3.3 Connectors
          4. 8.2.6.3.4 Guard Ring on PCB Edges
          5. 8.2.6.3.5 Analog and Digital Ground
    3. 8.3 Core Power Domains
      1. 8.3.1 General Constraints and Theory
      2. 8.3.2 Voltage Decoupling
      3. 8.3.3 Static PDN Analysis
      4. 8.3.4 Dynamic PDN Analysis
      5. 8.3.5 Power Supply Mapping
      6. 8.3.6 DPLL Voltage Requirement
      7. 8.3.7 Loss of Input Power Event
      8. 8.3.8 Example PCB Design
        1. 8.3.8.1 Example Stack-up
        2. 8.3.8.2 vdd_mpu Example Analysis
    4. 8.4 Single-Ended Interfaces
      1. 8.4.1 General Routing Guidelines
      2. 8.4.2 QSPI Board Design and Layout Guidelines
    5. 8.5 Differential Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1 Background
        2. 8.5.2.2 USB PHY Layout Guide
          1. 8.5.2.2.1 General Routing and Placement
          2. 8.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3  Board Stackup
            4. 8.5.2.2.2.4  Cable Connector Socket
            5. 8.5.2.2.2.5  Clock Routings
            6. 8.5.2.2.2.6  Crystals/Oscillator
            7. 8.5.2.2.2.7  DP/DM Trace
            8. 8.5.2.2.2.8  DP/DM Vias
            9. 8.5.2.2.2.9  Image Planes
            10. 8.5.2.2.2.10 JTAG Interface
            11. 8.5.2.2.2.11 Power Regulators
        3. 8.5.2.3 Electrostatic Discharge (ESD)
          1. 8.5.2.3.1 IEC ESD Stressing Test
            1. 8.5.2.3.1.1 Test Mode
            2. 8.5.2.3.1.2 Air Discharge Mode
            3. 8.5.2.3.1.3 Test Type
          2. 8.5.2.3.2 TI Component Level IEC ESD Test
          3. 8.5.2.3.3 Construction of a Custom USB Connector
          4. 8.5.2.3.4 ESD Protection System Design Consideration
        4. 8.5.2.4 References
      3. 8.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1 USB 3.0 interface introduction
        2. 8.5.3.2 USB 3.0 General routing rules
      4. 8.5.4 HDMI Board Design and Layout Guidelines
        1. 8.5.4.1 HDMI Interface Schematic
        2. 8.5.4.2 TMDS General Routing Guidelines
        3. 8.5.4.3 TPD5S115
        4. 8.5.4.4 HDMI ESD Protection Device (Required)
        5. 8.5.4.5 PCB Stackup Specifications
        6. 8.5.4.6 Grounding
      5. 8.5.5 SATA Board Design and Layout Guidelines
        1. 8.5.5.1 SATA Interface Schematic
        2. 8.5.5.2 Compatible SATA Components and Modes
        3. 8.5.5.3 PCB Stackup Specifications
        4. 8.5.5.4 Routing Specifications
      6. 8.5.6 PCIe Board Design and Layout Guidelines
        1. 8.5.6.1 PCIe Connections and Interface Compliance
          1. 8.5.6.1.1 Coupling Capacitors
          2. 8.5.6.1.2 Polarity Inversion
        2. 8.5.6.2 Non-standard PCIe connections
          1. 8.5.6.2.1 PCB Stackup Specifications
          2. 8.5.6.2.2 Routing Specifications
            1. 8.5.6.2.2.1 Impedance
            2. 8.5.6.2.2.2 Differential Coupling
            3. 8.5.6.2.2.3 Pair Length Matching
        3. 8.5.6.3 LJCB_REFN/P Connections
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
    7. 8.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 8.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 8.7.2 DDR2 Board Design and Layout Guidelines
        1. 8.7.2.1 Board Designs
        2. 8.7.2.2 DDR2 Interface
          1. 8.7.2.2.1  DDR2 Interface Schematic
          2. 8.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 8.7.2.2.3  PCB Stackup
          4. 8.7.2.2.4  Placement
          5. 8.7.2.2.5  DDR2 Keepout Region
          6. 8.7.2.2.6  Bulk Bypass Capacitors
          7. 8.7.2.2.7  High-Speed Bypass Capacitors
          8. 8.7.2.2.8  Net Classes
          9. 8.7.2.2.9  DDR2 Signal Termination
          10. 8.7.2.2.10 VREF Routing
        3. 8.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 8.7.3 DDR3 Board Design and Layout Guidelines
        1. 8.7.3.1  Board Designs
          1. 8.7.3.1.1 DDR3 versus DDR2
        2. 8.7.3.2  DDR3 EMIFs
        3. 8.7.3.3  DDR3 Device Combinations
        4. 8.7.3.4  DDR3 Interface Schematic
          1. 8.7.3.4.1 32-Bit DDR3 Interface
          2. 8.7.3.4.2 16-Bit DDR3 Interface
        5. 8.7.3.5  Compatible JEDEC DDR3 Devices
        6. 8.7.3.6  PCB Stackup
        7. 8.7.3.7  Placement
        8. 8.7.3.8  DDR3 Keepout Region
        9. 8.7.3.9  Bulk Bypass Capacitors
        10. 8.7.3.10 High-Speed Bypass Capacitors
          1. 8.7.3.10.1 Return Current Bypass Capacitors
        11. 8.7.3.11 Net Classes
        12. 8.7.3.12 DDR3 Signal Termination
        13. 8.7.3.13 VREF_DDR Routing
        14. 8.7.3.14 VTT
        15. 8.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.3.15.1 Four DDR3 Devices
            1. 8.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.3.15.2 Two DDR3 Devices
            1. 8.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.3.15.3 One DDR3 Device
            1. 8.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.3.16 Data Topologies and Routing Definition
          1. 8.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.3.17 Routing Specification
          1. 8.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.7.3.17.2 DQS and DQ Routing Specification
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABC|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.4.1 Video Input Ports (VIP)

NOTE

For more information, see the Video Input Port (VIP) section of the device TRM.

CAUTION

The I/O timings provided in Section 7, Timing Requirements and Switching Characteristics are applicable for all combinations of signals for vin1, vin5 and vin6. However, the timings are only valid for vin2, vin3, and vin4 if signals within a single IOSET are used. The IOSETs are defined in the Table 7-4, Table 7-5 and Table 7-6.

Table 4-4 VIP Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Video Input 1
vin1a_clk0 Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video capture. Input data is sampled on the CLK0 edge. I AG8
vin1a_de0 Video Input 1 Data Enable input (1) I AD9
vin1a_fld0 Video Input 1 Port A Field ID input (1) I AF9
vin1a_hsync0 Video Input 1 Port A Horizontal Sync input (1) I AE9
vin1a_vsync0 Video Input 1 Port A Vertical Sync input (1) I AF8
vin1a_d0 Video Input 1 Port A Data input (1) I AE8
vin1a_d1 Video Input 1 Port A Data input (1) I AD8
vin1a_d2 Video Input 1 Port A Data input (1) I AG7
vin1a_d3 Video Input 1 Port A Data input (1) I AH6
vin1a_d4 Video Input 1 Port A Data input (1) I AH3
vin1a_d5 Video Input 1 Port A Data input (1) I AH5
vin1a_d6 Video Input 1 Port A Data input (1) I AG6
vin1a_d7 Video Input 1 Port A Data input (1) I AH4
vin1a_d8 Video Input 1 Port A Data input (1) I AG4
vin1a_d9 Video Input 1 Port A Data input (1) I AG2
vin1a_d10 Video Input 1 Port A Data input (1) I AG3
vin1a_d11 Video Input 1 Port A Data input (1) I AG5
vin1a_d12 Video Input 1 Port A Data input (1) I AF2
vin1a_d13 Video Input 1 Port A Data input (1) I AF6
vin1a_d14 Video Input 1 Port A Data input (1) I AF3
vin1a_d15 Video Input 1 Port A Data input (1) I AF4
vin1a_d16 Video Input 1 Port A Data input (1) I AF1
vin1a_d17 Video Input 1 Port A Data input (1) I AE3
vin1a_d18 Video Input 1 Port A Data input (1) I AE5
vin1a_d19 Video Input 1 Port A Data input (1) I AE1
vin1a_d20 Video Input 1 Port A Data input (1) I AE2
vin1a_d21 Video Input 1 Port A Data input (1) I AE6
vin1a_d22 Video Input 1 Port A Data input (1) I AD2
vin1a_d23 Video Input 1 Port A Data input (1) I AD3
vin1b_hsync1 Video Input 1 Port B Horizontal Sync input (1) I N6 / AD9
vin1b_vsync1 Video Input 1 Port B Vertical Sync input (1) I AF9
vin1b_fld1 Video Input 1 Port B Field ID input (1) I AE9
vin1b_de1 Video Input 1 Port B Data Enable input (1) I AF8 / M4
vin1b_clk1 Video Input 1 Port B Clock input (1) I AH7
vin1b_d0 Video Input 1 Port B Data input (1) I AF4 / AD3
vin1b_d1 Video Input 1 Port B Data input (1) I AF3 / AD2
vin1b_d2 Video Input 1 Port B Data input (1) I AF6 / AE6
vin1b_d3 Video Input 1 Port B Data input (1) I AF2 / AE2
vin1b_d4 Video Input 1 Port B Data input (1) I AG5 / AE1
vin1b_d5 Video Input 1 Port B Data input (1) I AG3 / AE5
vin1b_d6 Video Input 1 Port B Data input (1) I AG2 / AE3
vin1b_d7 Video Input 1 Port B Data input (1) I AG4 / AF1
Video Input 2
vin2a_clk0 Video Input 2 Port A Clock input. I E1 / V1
vin2a_de0 Video Input 2 Port A Data Enable input I G2 / V7
vin2a_fld0 Video Input 2 Port A Field ID input I H7 / G2 / W2
vin2a_hsync0 Video Input 2 Port A Horizontal Sync input I G1 / U7
vin2a_vsync0 Video Input 2 Port A Vertical Sync input I G6 / V6
vin2a_d0 Video Input 2 Port A Data input I F2 / U4
vin2a_d1 Video Input 2 Port A Data input I F3 / V2
vin2a_d2 Video Input 2 Port A Data input I D1 / Y1
vin2a_d3 Video Input 2 Port A Data input I E2 / W9
vin2a_d4 Video Input 2 Port A Data input I D2 / V9
vin2a_d5 Video Input 2 Port A Data input I F4 / U5
vin2a_d6 Video Input 2 Port A Data input I C1 / V5
vin2a_d7 Video Input 2 Port A Data input I E4 / V4
vin2a_d8 Video Input 2 Port A Data input I F5 / V3
vin2a_d9 Video Input 2 Port A Data input I E6 / Y2
vin2a_d10 Video Input 2 Port A Data input I D3 / U6
vin2a_d11 Video Input 2 Port A Data input I F6 / U3
vin2a_d12 Video Input 2 Port A Data input I D5
vin2a_d13 Video Input 2 Port A Data input I C2
vin2a_d14 Video Input 2 Port A Data input I C3
vin2a_d15 Video Input 2 Port A Data input I C4
vin2a_d16 Video Input 2 Port A Data input I B2
vin2a_d17 Video Input 2 Port A Data input I D6
vin2a_d18 Video Input 2 Port A Data input I C5
vin2a_d19 Video Input 2 Port A Data input I A3
vin2a_d20 Video Input 2 Port A Data input I B3
vin2a_d21 Video Input 2 Port A Data input I B4
vin2a_d22 Video Input 2 Port A Data input I B5
vin2a_d23 Video Input 2 Port A Data input I A4
vin2b_clk1 Video Input 2 Port B Clock input I AB5 / H7
vin2b_de1 Video Input 2 Port B Data Enable input I AB8 / G2
vin2b_fld1 Video Input 2 Port B Field ID input I G2
vin2b_hsync1 Video Input 2 Port B Horizontal Sync input I AC5 / G1
vin2b_vsync1 Video Input 2 Port B Vertical Sync input I AB4 / G6
vin2b_d0 Video Input 2 Port B Data input I AD6 / A4
vin2b_d1 Video Input 2 Port B Data input I AC8 / B5
vin2b_d2 Video Input 2 Port B Data input I AC3 / B4
vin2b_d3 Video Input 2 Port B Data input I AC9 / B3
vin2b_d4 Video Input 2 Port B Data input I AC6 / A3
vin2b_d5 Video Input 2 Port B Data input I AC7 / C5
vin2b_d6 Video Input 2 Port B Data input I AC4 / D6
vin2b_d7 Video Input 2 Port B Data input I AD4 / B2
Video Input 3
vin3a_clk0 Video Input 3 Port A Clock input I B11 / AH7 / P1
vin3a_de0 Video Input 3 Port A Data Enable input I N9 / B3 / B10
vin3a_fld0 Video Input 3 Port A Field ID input I P9 / B4 / D11
vin3a_hsync0 Video Input 3 Port A Horizontal Sync input I N7 / B5 / C11
vin3a_vsync0 Video Input 3 Port A Vertical Sync input I R4 / A4 / E11
vin3a_d0 Video Input 3 Port A Data input I M6 / AF1 / B7
vin3a_d1 Video Input 3 Port A Data input I M2 / AE3 / B8
vin3a_d2 Video Input 3 Port A Data input I L5 / AE5 / A7
vin3a_d3 Video Input 3 Port A Data input I M1 / AE1 / A8
vin3a_d4 Video Input 3 Port A Data input I L6 / AE2 / C9
vin3a_d5 Video Input 3 Port A Data input I L4 / AE6 / A9
vin3a_d6 Video Input 3 Port A Data input I L3 / AD2 / B9
vin3a_d7 Video Input 3 Port A Data input I L2 / AD3 / A10
vin3a_d8 Video Input 3 Port A Data input I L1 / B2 / E8
vin3a_d9 Video Input 3 Port A Data input I K2 / D6 / D9
vin3a_d10 Video Input 3 Port A Data input I J1 / C5 / D7
vin3a_d11 Video Input 3 Port A Data input I J2 / A3 / D8
vin3a_d12 Video Input 3 Port A Data input I H1 / B3 / A5
vin3a_d13 Video Input 3 Port A Data input I J3 / B4 / C6
vin3a_d14 Video Input 3 Port A Data input I H2 / B5 / C8
vin3a_d15 Video Input 3 Port A Data input I H3 / A4 / C7
vin3a_d16 Video Input 3 Port A Data input I R6 / F11
vin3a_d17 Video Input 3 Port A Data input I T9 / G10
vin3a_d18 Video Input 3 Port A Data input I T6 / F10
vin3a_d19 Video Input 3 Port A Data input I T7 / G11
vin3a_d20 Video Input 3 Port A Data input I P6 / E9
vin3a_d21 Video Input 3 Port A Data input I R9 / F9
vin3a_d22 Video Input 3 Port A Data input I R5 / F8
vin3a_d23 Video Input 3 Port A Data input I P5 / E7
vin3b_clk1 Video Input 3 Port B Clock input I P7 / M4
vin3b_de1 Video Input 3 Port B Data Enable input I N6
vin3b_fld1 Video Input 3 Port A Field ID input I M4
vin3b_hsync1 Video Input 3 Port A Horizontal Sync input I H5
vin3b_vsync1 Video Input 3 Port A Vertical Sync input I H6
vin3b_d0 Video Input 3 Port B Data input I K7
vin3b_d1 Video Input 3 Port B Data input I M7
vin3b_d2 Video Input 3 Port B Data input I J5
vin3b_d3 Video Input 3 Port B Data input I K6
vin3b_d4 Video Input 3 Port B Data input I J7
vin3b_d5 Video Input 3 Port B Data input I J4
vin3b_d6 Video Input 3 Port B Data input I J6
vin3b_d7 Video Input 3 Port B Data input I H4
Video Input 4
vin4a_clk0 Video Input 4 Port A Clock input I P4 / B26 / B11
vin4a_de0 Video Input 4 Port A Data Enable input I H6 / C23 / B10 / P7
vin4a_fld0 Video Input 4 Port A Field ID input I J7 / F21 / P9 / D11
vin4a_hsync0 Video Input 4 Port A Horizontal Sync input I R3 / E21 / C11 / P7
vin4a_vsync0 Video Input 4 Port A Vertical Sync input I T2 / F20 / E11 / N1
vin4a_d0 Video Input 4 Port A Data input I R6 / B7 / B14
vin4a_d1 Video Input 4 Port A Data input I T9 / B8 / J14
vin4a_d2 Video Input 4 Port A Data input I T6 / A7 / G13
vin4a_d3 Video Input 4 Port A Data input I T7 / A8 / J11
vin4a_d4 Video Input 4 Port A Data input I P6 / C9 / E12
vin4a_d5 Video Input 4 Port A Data input I R9 / A9 / F13
vin4a_d6 Video Input 4 Port A Data input I R5 / B9 / C12
vin4a_d7 Video Input 4 Port A Data input I P5 / A10 / D12
vin4a_d8 Video Input 4 Port A Data input I E8 / U2 / E15
vin4a_d9 Video Input 4 Port A Data input I D9 / U1 / A20
vin4a_d10 Video Input 4 Port A Data input I D7 / P3 / B15
vin4a_d11 Video Input 4 Port A Data input I D8 / R2 / A15
vin4a_d12 Video Input 4 Port A Data input I A5 / K7 / D15
vin4a_d13 Video Input 4 Port A Data input I C6 / M7 / B16
vin4a_d14 Video Input 4 Port A Data input I C8 / J5 / B17
vin4a_d15 Video Input 4 Port A Data input I C7 / K6 / A17
vin4a_d16 Video Input 4 Port A Data input I C18 / F11
vin4a_d17 Video Input 4 Port A Data input I A21 / G10
vin4a_d18 Video Input 4 Port A Data input I G16 / F10
vin4a_d19 Video Input 4 Port A Data input I D17 / G11
vin4a_d20 Video Input 4 Port A Data input I AA3 / E9
vin4a_d21 Video Input 4 Port A Data input I AB9 / F9
vin4a_d22 Video Input 4 Port A Data input I AB3 / F8
vin4a_d23 Video Input 4 Port A Data input I AA4 / E7
vin4b_clk1 Video Input 4 Port B Clock input I N9 / V1
vin4b_de1 Video Input 4 Port B Data Enable input I P9 / V7
vin4b_fld1 Video Input 4 Port B Field ID input I P4 / W2
vin4b_hsync1 Video Input 4 Port B Horizontal Sync input I N7 / U7
vin4b_vsync1 Video Input 4 Port B Vertical Sync input I R4 / V6
vin4b_d0 Video Input 4 Port B Data input I R6 / U4
vin4b_d1 Video Input 4 Port B Data input I T9 / V2
vin4b_d2 Video Input 4 Port B Data input I T6 / Y1
vin4b_d3 Video Input 4 Port B Data input I T7 / W9
vin4b_d4 Video Input 4 Port B Data input I P6 / V9
vin4b_d5 Video Input 4 Port B Data input I R9 / U5
vin4b_d6 Video Input 4 Port B Data input I R5 / V5
vin4b_d7 Video Input 4 Port B Data input I P5 / V4
Video Input 5
vin5a_clk0 Video Input 5 Port A Clock input (2) I AC5
vin5a_de0 Video Input 5 Port A Data Enable input (2) I AB4
vin5a_fld0 Video Input 5 Port A Field ID input (2) I C17
vin5a_hsync0 Video Input 5 Port A Horizontal Sync input (2) I AB8
vin5a_vsync0 Video Input 5 Port A Vertical Sync input (2) I AB5
vin5a_d0 Video Input 5 Port A Data input (2) I AD6
vin5a_d1 Video Input 5 Port A Data input (2) I AC8
vin5a_d2 Video Input 5 Port A Data input (2) I AC3
vin5a_d3 Video Input 5 Port A Data input (2) I AC9
vin5a_d4 Video Input 5 Port A Data input (2) I AC6
vin5a_d5 Video Input 5 Port A Data input (2) I AC7
vin5a_d6 Video Input 5 Port A Data input (2) I AC4
vin5a_d7 Video Input 5 Port A Data input (2) I AD4
vin5a_d8 Video Input 5 Port A Data input (2) I AA4
vin5a_d9 Video Input 5 Port A Data input (2) I AB3
vin5a_d10 Video Input 5 Port A Data input (2) I AB9
vin5a_d11 Video Input 5 Port A Data input (2) I AA3
vin5a_d12 Video Input 5 Port A Data input (2) I D17
vin5a_d13 Video Input 5 Port A Data input (2) I G16
vin5a_d14 Video Input 5 Port A Data input (2) I A21
vin5a_d15 Video Input 5 Port A Data input (2) I C18
Video Input 6
vin6a_clk0 Video Input 6 Port A Clock input (2) I E17
vin6a_de0 Video Input 6 Port B Data Enable input (2) I D14
vin6a_fld0 Video Input 6 Port A Field ID input (2) I C14
vin6a_hsync0 Video Input 6 Port A Horizontal Sync input (2) I F12
vin6a_vsync0 Video Input 6 Port A Vertical Sync input (2) I G12
vin6a_d0 Video Input 6 Port A Data input (2) I C17 / D18
vin6a_d1 Video Input 6 Port A Data input (2) I B19
vin6a_d2 Video Input 6 Port A Data input (2) I F15
vin6a_d3 Video Input 6 Port A Data input (2) I B18
vin6a_d4 Video Input 6 Port A Data input (2) I A16
vin6a_d5 Video Input 6 Port A Data input (2) I C15
vin6a_d6 Video Input 6 Port A Data input (2) I A18
vin6a_d7 Video Input 6 Port A Data input (2) I A19
vin6a_d8 Video Input 6 Port A Data input (2) I F14
vin6a_d9 Video Input 6 Port A Data input (2) I G14
vin6a_d10 Video Input 6 Port A Data input (2) I A13
vin6a_d11 Video Input 6 Port A Data input (2) I E14
vin6a_d12 Video Input 6 Port A Data input (2) I A12
vin6a_d13 Video Input 6 Port A Data input (2) I B13
vin6a_d14 Video Input 6 Port A Data input (2) I A11
vin6a_d15 Video Input 6 Port A Data input (2) I B12
  1. The VIP1 interface (Video Input 1a and Video Input 1b in Table 4-4) signal sets are NOT supported in the DRA74x device. For more details on the device differentiation, refer to the Table 3-1, Device Comparison.
  2. The VIP3 interface (Video Input 5 and Video Input 6 in Table 4-4) signal sets are NOT supported in the DRA74x device. For more details on the device differentiation, refer to the Table 3-1, Device Comparison.