SPRS993E March 2017 – December 2018 DRA76P , DRA77P
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Figure 7-47 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 7-48 the x16 DDR2 system schematic is identical except that the high-word DDR2 device is deleted.
When not using all or part of a DDR2 interface, the proper method of handling the unused pins is to tie off the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. The vdds_ddrx and ddrx_vref0 power supply pins need to be connected to their respective power supplies even if DDRx is not being used. All other DDR interface pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.