SPRS993E March   2017  – December 2018 DRA76P , DRA77P

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
    2. 3.2 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 SATA
      16. 4.3.16 PCIe
      17. 4.3.17 DCAN and MCAN
      18. 4.3.18 GMAC_SW
      19. 4.3.19 MLB
      20. 4.3.20 eMMC/SD/SDIO
      21. 4.3.21 GPIO
      22. 4.3.22 KBD
      23. 4.3.23 PWM
      24. 4.3.24 ATL
      25. 4.3.25 Test Interfaces
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 PRCM
        3. 4.3.26.3 SDMA
        4. 4.3.26.4 INTC
        5. 4.3.26.5 Observability
        6. 4.3.26.6 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  LVCMOS CSI2 DC Electrical Characteristics
      5. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      HDMIPHY DC Electrical Characteristics
      10. 5.7.2      USBPHY DC Electrical Characteristics
      11. 5.7.3      SATAPHY DC Electrical Characteristics
      12. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
          3. 5.10.4.4.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  Timers
        9. 5.10.6.9  I2C
          1. Table 5-60 Timing Requirements for I2C Input Timings
          2. Table 5-61 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-62 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        10. 5.10.6.10 HDQ1W
          1. 5.10.6.10.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.10.2 HDQ/1-Wire—1-Wire Mode
        11. 5.10.6.11 UART
          1. Table 5-67 Timing Requirements for UART
          2. Table 5-68 Switching Characteristics Over Recommended Operating Conditions for UART
        12. 5.10.6.12 McSPI
        13. 5.10.6.13 QSPI
        14. 5.10.6.14 McASP
          1. Table 5-75 Timing Requirements for McASP1
          2. Table 5-76 Timing Requirements for McASP2
          3. Table 5-77 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-78 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-79 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-80 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        15. 5.10.6.15 USB
          1. 5.10.6.15.1 USB1 DRD PHY
          2. 5.10.6.15.2 USB2 PHY
          3. 5.10.6.15.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
        16. 5.10.6.16 SATA
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 CAN
          1. 5.10.6.18.1 DCAN
          2. 5.10.6.18.2 MCAN-FD
          3. Table 5-95  Timing Requirements for CANx Receive
          4. Table 5-96  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-97  Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-98  Timing Requirements for miin_txclk - MII Operation
            3. Table 5-99  Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-100 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-105 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-106 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-107 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-108 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-112 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-113 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-114 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-115 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit Data, SDR, Half-Cycle
            2. 5.10.6.21.1.2 High-Speed, 4-bit Data, SDR, Half-Cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit Data, Half-Cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit Data, Half-Cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit Data, Half-Cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit Data, Half-Cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit Data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit Data, Half Cycle
            2. 5.10.6.21.2.2 High-Speed JC64 SDR, 8-bit Data, Half Cycle
            3. 5.10.6.21.2.3 High-Speed HS200 JC64 SDR, 8-bit Data, Half Cycle
            4. 5.10.6.21.2.4 High-Speed JC64 DDR, 8-bit Data
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High-Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 ATL
          1. 5.10.6.23.1 ATL Electrical Data/Timing
            1. Table 5-171 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
        24. 5.10.6.24 System and Miscellaneous Interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-172 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-173 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-174 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-175 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  ISS
    6. 6.6  IVA
    7. 6.7  EVE
    8. 6.8  IPU
    9. 6.9  VPE
    10. 6.10 GPU
    11. 6.11 ATL Overview
    12. 6.12 Memory Subsystem
      1. 6.12.1 EMIF
      2. 6.12.2 GPMC
      3. 6.12.3 ELM
      4. 6.12.4 OCMC
    13. 6.13 Interprocessor Communication
      1. 6.13.1 Mailbox
      2. 6.13.2 Spinlock
    14. 6.14 Interrupt Controller
    15. 6.15 EDMA
    16. 6.16 Peripherals
      1. 6.16.1  VIP
      2. 6.16.2  DSS
      3. 6.16.3  Timers
      4. 6.16.4  I2C
      5. 6.16.5  HDQ1W
      6. 6.16.6  UART
        1. 6.16.6.1 UART Features
        2. 6.16.6.2 IrDA Features
        3. 6.16.6.3 CIR Features
      7. 6.16.7  McSPI
      8. 6.16.8  QSPI
      9. 6.16.9  McASP
      10. 6.16.10 USB
      11. 6.16.11 SATA
      12. 6.16.12 PCIe
      13. 6.16.13 CAN
      14. 6.16.14 GMAC_SW
      15. 6.16.15 MLB
      16. 6.16.16 CSI2
        1. 6.16.16.1 CSI-2 MIPI D-PHY
      17. 6.16.17 eMMC/SD/SDIO
      18. 6.16.18 GPIO
      19. 6.16.19 ePWM
      20. 6.16.20 eCAP
      21. 6.16.21 eQEP
    17. 6.17 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_mpu Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 JTAG Interface
            11. 7.5.2.2.2.11 Power Regulators
        3. 7.5.2.3 Electrostatic Discharge (ESD)
          1. 7.5.2.3.1 IEC ESD Stressing Test
            1. 7.5.2.3.1.1 Test Mode
            2. 7.5.2.3.1.2 Air Discharge Mode
            3. 7.5.2.3.1.3 Test Type
          2. 7.5.2.3.2 TI Component Level IEC ESD Test
          3. 7.5.2.3.3 Construction of a Custom USB Connector
          4. 7.5.2.3.4 ESD Protection System Design Consideration
        4. 7.5.2.4 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 SATA Board Design and Layout Guidelines
        1. 7.5.5.1 SATA Interface Schematic
        2. 7.5.5.2 Compatible SATA Components and Modes
        3. 7.5.5.3 PCB Stackup Specifications
        4. 7.5.5.4 Routing Specifications
      6. 7.5.6 PCIe Board Design and Layout Guidelines
        1. 7.5.6.1 PCIe Connections and Interface Compliance
          1. 7.5.6.1.1 Coupling Capacitors
          2. 7.5.6.1.2 Polarity Inversion
        2. 7.5.6.2 Non-standard PCIe connections
          1. 7.5.6.2.1 PCB Stackup Specifications
          2. 7.5.6.2.2 Routing Specifications
            1. 7.5.6.2.2.1 Impedance
            2. 7.5.6.2.2.2 Differential Coupling
            3. 7.5.6.2.2.3 Pair Length Matching
        3. 7.5.6.3 LJCB_REFN/P Connections
      7. 7.5.7 CSI2 Board Design and Routing Guidelines
        1. 7.5.7.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.7.1.1 General Guidelines
          2. 7.5.7.1.2 Length Mismatch Guidelines
            1. 7.5.7.1.2.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.7.1.3 Frequency-domain Specification Guidelines
    6. 7.6 DDR2/DDR3 Board Design and Layout Guidelines
      1. 7.6.1 DDR2/DDR3 General Board Layout Guidelines
      2. 7.6.2 DDR2 Board Design and Layout Guidelines
        1. 7.6.2.1 Board Designs
        2. 7.6.2.2 DDR2 Interface
          1. 7.6.2.2.1  DDR2 Interface Schematic
          2. 7.6.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.6.2.2.3  PCB Stackup
          4. 7.6.2.2.4  Placement
          5. 7.6.2.2.5  DDR2 Keepout Region
          6. 7.6.2.2.6  Bulk Bypass Capacitors
          7. 7.6.2.2.7  High-Speed Bypass Capacitors
          8. 7.6.2.2.8  Net Classes
          9. 7.6.2.2.9  DDR2 Signal Termination
          10. 7.6.2.2.10 VREF Routing
        3. 7.6.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 7.6.3 DDR3 Board Design and Layout Guidelines
        1. 7.6.3.1  Board Designs
        2. 7.6.3.2  DDR3 EMIF
        3. 7.6.3.3  DDR3 Device Combinations
        4. 7.6.3.4  DDR3 Interface Schematic
          1. 7.6.3.4.1 32-Bit DDR3 Interface
          2. 7.6.3.4.2 16-Bit DDR3 Interface
        5. 7.6.3.5  Compatible JEDEC DDR3 Devices
        6. 7.6.3.6  PCB Stackup
        7. 7.6.3.7  Placement
        8. 7.6.3.8  DDR3 Keepout Region
        9. 7.6.3.9  Bulk Bypass Capacitors
        10. 7.6.3.10 High-Speed Bypass Capacitors
          1. 7.6.3.10.1 Return Current Bypass Capacitors
        11. 7.6.3.11 Net Classes
        12. 7.6.3.12 DDR3 Signal Termination
        13. 7.6.3.13 VREF_DDR Routing
        14. 7.6.3.14 VTT
        15. 7.6.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.6.3.15.1 Four DDR3 Devices
            1. 7.6.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.6.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.6.3.15.2 Two DDR3 Devices
            1. 7.6.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.6.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.6.3.15.3 One DDR3 Device
            1. 7.6.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.6.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.6.3.16 Data Topologies and Routing Definition
          1. 7.6.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.6.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.6.3.17 Routing Specification
          1. 7.6.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.6.3.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1  Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2  Tools and Software
    3. 8.3  Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4  Receiving Notification of Documentation Updates
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ACD|784
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.3.21 GPIO

NOTE

For more information, see the General-Purpose Interface section of the Device TRM.

Table 4-22 GPIOs Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
GPIO 1
gpio1_0 General-Purpose Input I AB19
gpio1_1 General-Purpose Input I AC20
gpio1_2 General-Purpose Input I AB20
gpio1_3 General-Purpose Input I AB21
gpio1_4 General-Purpose Input/Output IO D15
gpio1_5 General-Purpose Input/Output IO A16
gpio1_6 General-Purpose Input/Output IO N5
gpio1_7 General-Purpose Input/Output IO M2
gpio1_8 General-Purpose Input/Output IO L5
gpio1_9 General-Purpose Input/Output IO M1
gpio1_10 General-Purpose Input/Output IO K6
gpio1_11 General-Purpose Input/Output IO L4
gpio1_12 General-Purpose Input/Output IO L3
gpio1_13 General-Purpose Input/Output IO L2
gpio1_14 General-Purpose Input/Output IO E19
gpio1_15 General-Purpose Input/Output IO D19
gpio1_16 General-Purpose Input/Output IO F20
gpio1_17 General-Purpose Input/Output IO C22
gpio1_18 General-Purpose Input/Output IO H1
gpio1_19 General-Purpose Input/Output IO K2
gpio1_20 General-Purpose Input/Output IO H2
gpio1_21 General-Purpose Input/Output IO K3
gpio1_22 General-Purpose Input/Output IO AA6
gpio1_23 General-Purpose Input/Output IO AB5
gpio1_24 General-Purpose Input/Output IO AB7
gpio1_25 General-Purpose Input/Output IO AA5
gpio1_26 General-Purpose Input/Output IO M6
gpio1_27 General-Purpose Input/Output IO K4
gpio1_28 General-Purpose Input/Output IO P5
gpio1_29 General-Purpose Input/Output IO N6
gpio1_30 General-Purpose Input/Output IO N4
gpio1_31 General-Purpose Input/Output IO R3
GPIO 2
gpio2_0 General-Purpose Input/Output IO J5
gpio2_1 General-Purpose Input/Output IO K5
gpio2_2 General-Purpose Input/Output IO P4
gpio2_3 General-Purpose Input/Output IO R2
gpio2_4 General-Purpose Input/Output IO R6
gpio2_5 General-Purpose Input/Output IO T2
gpio2_6 General-Purpose Input/Output IO U1
gpio2_7 General-Purpose Input/Output IO P3
gpio2_8 General-Purpose Input/Output IO R1
gpio2_9 General-Purpose Input/Output IO H6
gpio2_10 General-Purpose Input/Output IO G6
gpio2_11 General-Purpose Input/Output IO J4
gpio2_12 General-Purpose Input/Output IO F5
gpio2_13 General-Purpose Input/Output IO G5
gpio2_14 General-Purpose Input/Output IO J3
gpio2_15 General-Purpose Input/Output IO H4
gpio2_16 General-Purpose Input/Output IO H3
gpio2_17 General-Purpose Input/Output IO H5
gpio2_18 General-Purpose Input/Output IO G4
gpio2_19 General-Purpose Input/Output IO T1
gpio2_20 General-Purpose Input/Output IO P2
gpio2_21 General-Purpose Input/Output IO P1
gpio2_22 General-Purpose Input/Output IO L6
gpio2_23 General-Purpose Input/Output IO N1
gpio2_24 General-Purpose Input/Output IO M5
gpio2_25 General-Purpose Input/Output IO M3
gpio2_26 General-Purpose Input/Output IO N3
gpio2_27 General-Purpose Input/Output IO M4
gpio2_28 General-Purpose Input/Output IO N2
gpio2_29 General-Purpose Input/Output IO B16
gpio2_30 General-Purpose Input/Output IO AD8
gpio2_31 General-Purpose Input/Output IO AC8
GPIO 3
gpio3_0 General-Purpose Input/Output IO AC9
gpio3_1 General-Purpose Input/Output IO AD9
gpio3_2 General-Purpose Input/Output IO AC10
gpio3_3 General-Purpose Input/Output IO AD7
gpio3_4 General-Purpose Input/Output IO AE9
gpio3_5 General-Purpose Input/Output IO AF10
gpio3_6 General-Purpose Input/Output IO AE7
gpio3_7 General-Purpose Input/Output IO AE8
gpio3_8 General-Purpose Input/Output IO AE6
gpio3_9 General-Purpose Input/Output IO AF7
gpio3_10 General-Purpose Input/Output IO AF8
gpio3_11 General-Purpose Input/Output IO AF6
gpio3_12 General-Purpose Input/Output IO AF4
gpio3_13 General-Purpose Input/Output IO AF2
gpio3_14 General-Purpose Input/Output IO AF3
gpio3_15 General-Purpose Input/Output IO AF5
gpio3_16 General-Purpose Input/Output IO AE5
gpio3_17 General-Purpose Input/Output IO AF1
gpio3_18 General-Purpose Input/Output IO AD6
gpio3_19 General-Purpose Input/Output IO AE3
gpio3_20 General-Purpose Input/Output IO AE4
gpio3_21 General-Purpose Input/Output IO AE1
gpio3_22 General-Purpose Input/Output IO AD5
gpio3_23 General-Purpose Input/Output IO AD3
gpio3_24 General-Purpose Input/Output IO AD4
gpio3_25 General-Purpose Input/Output IO AE2
gpio3_26 General-Purpose Input/Output IO AD1
gpio3_27 General-Purpose Input/Output IO AD2
gpio3_28 General-Purpose Input/Output IO F1
gpio3_29 General-Purpose Input/Output IO G2
gpio3_30 General-Purpose Input/Output IO D5
gpio3_31 General-Purpose Input/Output IO G1
GPIO 4
gpio4_0 General-Purpose Input/Output IO E5
gpio4_1 General-Purpose Input/Output IO F2
gpio4_2 General-Purpose Input/Output IO E3
gpio4_3 General-Purpose Input/Output IO E1
gpio4_4 General-Purpose Input/Output IO E2
gpio4_5 General-Purpose Input/Output IO D2
gpio4_6 General-Purpose Input/Output IO F3
gpio4_7 General-Purpose Input/Output IO D1
gpio4_8 General-Purpose Input/Output IO E4
gpio4_9 General-Purpose Input/Output IO G3
gpio4_10 General-Purpose Input/Output IO C5
gpio4_11 General-Purpose Input/Output IO D3
gpio4_12 General-Purpose Input/Output IO F4
gpio4_13 General-Purpose Input/Output IO E6
gpio4_14 General-Purpose Input/Output IO C1
gpio4_15 General-Purpose Input/Output IO C2
gpio4_16 General-Purpose Input/Output IO C3
gpio4_17 General-Purpose Input/Output IO A12
gpio4_18 General-Purpose Input/Output IO D14
gpio4_19 General-Purpose Input/Output IO D11
gpio4_20 General-Purpose Input/Output IO C10
gpio4_21 General-Purpose Input/Output IO B10
gpio4_22 General-Purpose Input/Output IO A10
gpio4_23 General-Purpose Input/Output IO D10
gpio4_24 General-Purpose Input/Output IO B2
gpio4_25 General-Purpose Input/Output IO B5
gpio4_26 General-Purpose Input/Output IO D4
gpio4_27 General-Purpose Input/Output IO A3
gpio4_28 General-Purpose Input/Output IO B3
gpio4_29 General-Purpose Input/Output IO B4
gpio4_30 General-Purpose Input/Output IO C4
gpio4_31 General-Purpose Input/Output IO A4
GPIO 5
gpio5_0 General-Purpose Input/Output IO A13
gpio5_1 General-Purpose Input/Output IO F14
gpio5_2 General-Purpose Input/Output IO F10
gpio5_3 General-Purpose Input/Output IO F11
gpio5_4 General-Purpose Input/Output IO E13
gpio5_5 General-Purpose Input/Output IO E11
gpio5_6 General-Purpose Input/Output IO E12
gpio5_7 General-Purpose Input/Output IO D13
gpio5_8 General-Purpose Input/Output IO C11
gpio5_9 General-Purpose Input/Output IO D12
gpio5_10 General-Purpose Input/Output IO B11
gpio5_11 General-Purpose Input/Output IO A11
gpio5_12 General-Purpose Input/Output IO C12
gpio5_13 General-Purpose Input/Output IO B17
gpio5_14 General-Purpose Input/Output IO F13
gpio5_15 General-Purpose Input/Output IO V1
gpio5_16 General-Purpose Input/Output IO U3
gpio5_17 General-Purpose Input/Output IO U2
gpio5_18 General-Purpose Input/Output IO V2
gpio5_19 General-Purpose Input/Output IO Y1
gpio5_20 General-Purpose Input/Output IO T6
gpio5_21 General-Purpose Input/Output IO U5
gpio5_22 General-Purpose Input/Output IO T4
gpio5_23 General-Purpose Input/Output IO T3
gpio5_24 General-Purpose Input/Output IO U6
gpio5_25 General-Purpose Input/Output IO T5
gpio5_26 General-Purpose Input/Output IO U4
gpio5_27 General-Purpose Input/Output IO V4
gpio5_28 General-Purpose Input/Output IO W2
gpio5_29 General-Purpose Input/Output IO V3
gpio5_30 General-Purpose Input/Output IO Y2
gpio5_31 General-Purpose Input/Output IO W1
GPIO 6
gpio6_4 General-Purpose Input/Output IO B12
gpio6_5 General-Purpose Input/Output IO F12
gpio6_6 General-Purpose Input/Output IO E14
gpio6_7 General-Purpose Input/Output IO B15
gpio6_8 General-Purpose Input/Output IO C14
gpio6_9 General-Purpose Input/Output IO A15
gpio6_10 General-Purpose Input/Output IO AC5
gpio6_11 General-Purpose Input/Output IO AB4
gpio6_12 General-Purpose Input/Output IO AD12
gpio6_13 General-Purpose Input/Output IO AC11
gpio6_14 General-Purpose Input/Output IO E21
gpio6_15 General-Purpose Input/Output IO F17
gpio6_16 General-Purpose Input/Output IO F18
gpio6_17 General-Purpose Input/Output IO D18
gpio6_18 General-Purpose Input/Output IO E17
gpio6_19 General-Purpose Input/Output IO B25
gpio6_20 General-Purpose Input/Output IO A22
gpio6_21 General-Purpose Input/Output IO W3
gpio6_22 General-Purpose Input/Output IO W5
gpio6_23 General-Purpose Input/Output IO V5
gpio6_24 General-Purpose Input/Output IO Y4
gpio6_25 General-Purpose Input/Output IO Y5
gpio6_26 General-Purpose Input/Output IO Y3
gpio6_27 General-Purpose Input/Output IO W4
gpio6_28 General-Purpose Input/Output IO V6
gpio6_29 General-Purpose Input/Output IO AC3
gpio6_30 General-Purpose Input/Output IO AC7
gpio6_31 General-Purpose Input/Output IO Y6
GPIO 7
gpio7_0 General-Purpose Input/Output IO W6
gpio7_1 General-Purpose Input/Output IO AC6
gpio7_2 General-Purpose Input/Output IO AC4
gpio7_3 General-Purpose Input/Output IO P6
gpio7_4 General-Purpose Input/Output IO J6
gpio7_5 General-Purpose Input/Output IO R4
gpio7_6 General-Purpose Input/Output IO R5
gpio7_7 General-Purpose Input/Output IO A24
gpio7_8 General-Purpose Input/Output IO C15
gpio7_9 General-Purpose Input/Output IO B24
gpio7_10 General-Purpose Input/Output IO A23
gpio7_11 General-Purpose Input/Output IO A21
gpio7_12 General-Purpose Input/Output IO B20
gpio7_13 General-Purpose Input/Output IO B19
gpio7_14 General-Purpose Input/Output IO A25
gpio7_15 General-Purpose Input/Output IO B21
gpio7_16 General-Purpose Input/Output IO E16
gpio7_17 General-Purpose Input/Output IO B23
gpio7_18 General-Purpose Input/Output IO L1
gpio7_19 General-Purpose Input/Output IO K1
gpio7_22 General-Purpose Input/Output IO F22
gpio7_23 General-Purpose Input/Output IO C21
gpio7_24 General-Purpose Input/Output IO F21
gpio7_25 General-Purpose Input/Output IO E23
gpio7_26 General-Purpose Input/Output IO D22
gpio7_27 General-Purpose Input/Output IO E22
gpio7_28 General-Purpose Input/Output IO J1
gpio7_29 General-Purpose Input/Output IO J2
gpio7_30 General-Purpose Input/Output IO C13
gpio7_31 General-Purpose Input/Output IO B13
GPIO 8
gpio8_0 General-Purpose Input/Output IO F9
gpio8_1 General-Purpose Input/Output IO E10
gpio8_2 General-Purpose Input/Output IO D9
gpio8_3 General-Purpose Input/Output IO C6
gpio8_4 General-Purpose Input/Output IO E9
gpio8_5 General-Purpose Input/Output IO F8
gpio8_6 General-Purpose Input/Output IO F7
gpio8_7 General-Purpose Input/Output IO E7
gpio8_8 General-Purpose Input/Output IO E8
gpio8_9 General-Purpose Input/Output IO D8
gpio8_10 General-Purpose Input/Output IO D6
gpio8_11 General-Purpose Input/Output IO D7
gpio8_12 General-Purpose Input/Output IO A5
gpio8_13 General-Purpose Input/Output IO B6
gpio8_14 General-Purpose Input/Output IO C8
gpio8_15 General-Purpose Input/Output IO C7
gpio8_16 General-Purpose Input/Output IO B7
gpio8_17 General-Purpose Input/Output IO B8
gpio8_18 General-Purpose Input/Output IO A6
gpio8_19 General-Purpose Input/Output IO A7
gpio8_20 General-Purpose Input/Output IO C9
gpio8_21 General-Purpose Input/Output IO A8
gpio8_22 General-Purpose Input/Output IO B9
gpio8_23 General-Purpose Input/Output IO A9
gpio8_27 General-Purpose Input I B22
gpio8_28 General-Purpose Input/Output IO C18
gpio8_29 General-Purpose Input/Output IO E18
gpio8_30 General-Purpose Input/Output IO F19
gpio8_31 General-Purpose Input/Output IO C23