SPRS993E March 2017 – December 2018 DRA76P , DRA77P
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Table 5-143 and Table 5-144 present timing requirements and switching characteristics for MMC2 - High-Speed SDR in receiver and transmitter mode (see Figure 5-94 and Figure 5-95).
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
JC643 | tsu(cmdV-clkH) | Setup time, mmc2_cmd valid before mmc2_clk rising clock edge | 5.6 | ns | |
JC644 | th(clkH-cmdV) | Hold time, mmc2_cmd valid after mmc2_clk rising clock edge | 2.6 | ns | |
JC647 | tsu(dV-clkH) | Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge | 5.6 | ns | |
JC648 | th(clkH-dV) | Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge | 2.6 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
JC641 | fop(clk) | Operating frequency, mmc2_clk | 48 | MHz | |
JC642H | tw(clkH) | Pulse duration, mmc2_clk high | 0.5P-0.172 (1) | ns | |
JC642L | tw(clkL) | Pulse duration, mmc2_clk low | 0.5P-0.172 (1) | ns | |
JC645 | td(clkL-cmdV) | Delay time, mmc2_clk falling clock edge to mmc2_cmd transition | -6.64 | 6.64 | ns |
JC646 | td(clkL-dV) | Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition | -6.64 | 6.64 | ns |