SPRS993E March 2017 – December 2018 DRA76P , DRA77P
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
For test and debug of the USB PHY only, an IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture (JTAG) and Serial Test and Configuration Interface (STCI) may be available on the System-on-Chip (SoC). If available, keep the USB PHY JTAG interface less than six inches; keeping this distance short reduces noise coupling from other devices and signal loss due to resistance.