SPRS993E March 2017 – December 2018 DRA76P , DRA77P
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM. Table 5-5 lists the clock source options for each module on this device, along with the maximum frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.
Module | Clock Sources | |||||
---|---|---|---|---|---|---|
Instance Name | Input Clock Name | Clock Type | Max. Clock Allowed (MHz) | PRCM Clock Name | PLL / OSC / Source Clock Name | PLL / OSC / Source Name |
AES1 | AES1_L3_CLK | Int | 266 | L4SEC_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
AES2 | AES2_L3_CLK | Int | 266 | L4SEC_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
ATL | ATL_ICLK_L3 | Int | 266 | ATL_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
ATLPCLK | Func | 266 | ATL_GFCLK | CORE_X2_CLK | DPLL_CORE | |
PER_ABE_X1_GFCLK | DPLL_ABE | |||||
FUNC_32K_CLK | OSC0 | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
BB2D | BB2D_FCLK | Func | 354.6 | BB2D_GFCLK | BB2D_GFCLK | DPLL_CORE |
BB2D_ICLK | Int | 266 | DSS_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
CSI2_0 | CTRLCLK | Int & Func | 96 | LVDSRX_96M_GFCLK | FUNC_192M_CLK | DPLL_PER |
CAL_FCLK | Int & Func | 266 | VIP3_GCLK | CORE_ISS_MAIN_ CLK | DPLL_CORE | |
L3_ICLK | CM_CORE_AON | |||||
CSI2_1 | CTRLCLK | Int & Func | 96 | LVDSRX_96M_GFCLK | FUNC_192M_CLK | DPLL_PER |
CAL_FCLK | Int & Func | 266 | VIP3_GCLK | CORE_ISS_MAIN_ CLK | DPLL_CORE | |
L3_ICLK | CM_CORE_AON | |||||
COUNTER_32K | COUNTER_32K_FCLK | Func | 0.032 | FUNC_32K_CLK | SYS_CLK1/610 | OSC0 |
COUNTER_32K_ICLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
CTRL_MODULE_BANDGAP | L3INSTR_TS_GCLK | Int | 4.8 | L3INSTR_TS_GCLK | SYS_CLK1 | OSC0 |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
CTRL_MODULE_CORE | L4CFG_L4_GICLK | Int | 133 | L4CFG_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
CTRL_MODULE_WKUP | WKUPAON_GICLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
DCAN1 | DCAN1_FCLK | Func | 38.4 | DCAN1_SYS_CLK | SYS_CLK1 | OSC0 |
SYS_CLK2 | OSC1 | |||||
DCAN1_ICLK | Int | 266 | WKUPAON_GICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
DCAN2 | DCAN2_FCLK | Func | 38.4 | DCAN2_SYS_CLK | SYS_CLK1 | OSC0 |
DCAN2_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
MCAN | MCAN_FCLK | Func | 38.4 | MCAN_SYS_CLK | SYS_CLK1 | OSC0 |
SYS_CLK2 | OSC1 | |||||
MCAN_ICLK | Int | 266 | WKUPAON_GICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
DES3DES | DES_CLK_L3 | Int | 266 | L4SEC_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
DLL | EMIF_DLL_FCLK | Func | EMIF_DLL_FCLK | EMIF_DLL_GCLK | EMIF_DLL_GCLK | DPLL_DDR |
DLL_AGING | FCLK | Int | 38.4 | L3INSTR_DLL_AGING_GCLK | SYS_CLK1 | OSC0 |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
DMA_CRYPTO | DMA_CRYPTO_FCLK | Int & Func | 266 | L4SEC_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
DMA_CRYPTO_ICLK | Int | 133 | L4SEC_L4_GICLK | CORE_X2_CLK | DPLL_CORE | |
DMM | DMM_CLK | Int | 266 | EMIF_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
DPLL_DEBUG | SYSCLK | Int | 38.4 | EMU_SYS_CLK | SYS_CLK1 | OSC0 |
DSP1 | DSP1_FICLK | Int & Func | DSP_CLK | DSP1_GFCLK | DSP_GFCLK | DPLL_DSP |
DSP2 | DSP2_FICLK | Int & Func | DSP_CLK | DSP2_GFCLK | DSP_GFCLK | DPLL_DSP |
DSS | DSS_HDMI_CEC_CLK | Func | 0.032 | HDMI_CEC_GFCLK | SYS_CLK1/610 | OSC0 |
DSS_HDMI_PHY_CLK | Func | 48 | HDMI_PHY_GFCLK | FUNC_192M_CLK | DPLL_PER | |
DSS_CLK | Func | 192 | DSS_GFCLK | DSS_CLK | DPLL_PER | |
HDMI_CLKINP | Func | 38.4 | HDMI_DPLL_CLK | SYS_CLK1 | OSC0 | |
SYS_CLK2 | OSC1 | |||||
DSS_L3_ICLK | Int | 266 | DSS_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
VIDEO1_CLKINP | Func | 38.4 | VIDEO1_DPLL_CLK | SYS_CLK1 | OSC0 | |
SYS_CLK2 | OSC1 | |||||
VIDEO2_CLKINP | Func | 38.4 | VIDEO2_DPLL_CLK | SYS_CLK1 | OSC0 | |
SYS_CLK2 | OSC1 | |||||
DPLL_DSI1_A_CLK1 | Func | 209.3 | N/A | HDMI_CLK | DPLL_HDMI | |
VIDEO1_CLKOUT1 | DPLL_VIDEO1 | |||||
DPLL_DSI1_B_CLK1 | Func | 209.3 | N/A | VIDEO1_CLKOUT3 | DPLL_VIDEO1 | |
VIDEO2_CLKOUT3 | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
DPLL_DSI1_C_CLK1 | Func | 209.3 | N/A | HDMI_CLK | DPLL_HDMI | |
VIDEO1_CLKOUT3 | DPLL_VIDEO1 | |||||
VIDEO2_CLKOUT1 | DPLL_VIDEO2 | |||||
DPLL_HDMI_CLK1 | Func | 185.6 | N/A | HDMI_CLK | DPLL_HDMI | |
DSS DISPC | LCD1_CLK | Func | 209.3 | N/A | DPLL_DSI1_A_CLK1 | See DSS data in the rows above |
DSS_CLK | ||||||
LCD2_CLK | Func | 209.3 | N/A | DPLL_DSI1_B_CLK1 | ||
DSS_CLK | ||||||
LCD3_CLK | Func | 209.3 | N/A | DPLL_DSI1_C_CLK1 | ||
DSS_CLK | ||||||
F_CLK | Func | 209.3 | N/A | DPLL_DSI1_A_CLK1 | ||
DPLL_DSI1_B_CLK1 | ||||||
DPLL_DSI1_C_CLK1 | ||||||
DSS_CLK | ||||||
DPLL_HDMI_CLK1 | ||||||
ISP | ISS_MAIN_FCLK | Func | ISP_CLK | CORE_ISS_MAIN_CLK | CORE_ISS_MAIN_CLK | DPLL_CORE |
PCLK | Func | ISS_MAIN_FCLK | ISS_MAIN_FCLK | |||
EFUSE_CTRL_CUST | ocp_clk | Int | 133 | CUSTEFUSE_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
sys_clk | Func | 38.4 | CUSTEFUSE_SYS_GFCLK | SYS_CLK1 | OSC0 | |
ELM | ELM_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
EMIF_OCP_FW | L3_CLK | Int | 266 | EMIF_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
EMIF_PHY1 | EMIF_PHY1_FCLK | Func | DDR | EMIF_PHY_GCLK | EMIF_PHY_GCLK | DPLL_DDR |
EMIF_PHY2 | EMIF_PHY2_FCLK | Func | DDR | EMIF_PHY_GCLK | EMIF_PHY_GCLK | DPLL_DDR |
EMIF1 | EMIF1_ICLK | Int | 266 | EMIF_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
EMIF2 | EMIF2_ICLK | Int | 266 | EMIF_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
EVE1 | EVE1_FCLK | Func | EVE_FCLK | EVE1_GFCLK | - | DPLL_DSP |
EVE_GFCLK | DPLL_EVE | |||||
EVE2 | EVE2_FCLK | Func | EVE_FCLK | EVE2_GFCLK | - | DPLL_DSP |
EVE_GFCLK | DPLL_EVE | |||||
FPKA | PKA_CLK | Int & Func | 266 | L4SEC_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
GMAC_SW | CPTS_RFT_CLK | Func | 266 | GMAC_RFT_CLK | PER_ABE_X1_GFCLK | DPLL_ABE |
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
CORE_X2_CLK | DPLL_CORE | |||||
MAIN_CLK | Int | 125 | GMAC_MAIN_CLK | GMAC_250M_CLK | DPLL_GMAC | |
MHZ_250_CLK | Func | 250 | GMII_250MHZ_CLK | GMII_250MHZ_CLK | DPLL_GMAC | |
MHZ_5_CLK | Func | 5 | RGMII_5MHZ_CLK | GMAC_RMII_HS_CLK | DPLL_GMAC | |
MHZ_50_CLK | Func | 50 | RMII_50MHZ_CLK | GMAC_RMII_HS_CLK | DPLL_GMAC | |
RMII1_MHZ_50_CLK | Func | 50 | RMII_50MHZ_CLK | GMAC_RMII_HS_CLK | DPLL_GMAC | |
RMII2_MHZ_50_CLK | Func | 50 | RMII_50MHZ_CLK | GMAC_RMII_HS_CLK | DPLL_GMAC | |
GPIO1 | GPIO1_ICLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
GPIO1_DBCLK | Func | 0.032 | WKUPAON_SYS_GFCLK | WKUPAON_32K_GFCLK | OSC0 | |
GPIO2 | GPIO2_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
GPIO2_DBCLK | Func | 0.032 | GPIO_GFCLK | FUNC_32K_CLK | OSC0 | |
GPIO3 | GPIO3_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
GPIO3_DBCLK | Func | 0.032 | GPIO_GFCLK | FUNC_32K_CLK | OSC0 | |
GPIO4 | GPIO4_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
GPIO4_DBCLK | Func | 0.032 | GPIO_GFCLK | FUNC_32K_CLK | OSC0 | |
PIDBCLK | Func | 0.032 | GPIO_GFCLK | |||
GPIO5 | GPIO5_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
GPIO5_DBCLK | Func | 0.032 | GPIO_GFCLK | FUNC_32K_CLK | OSC0 | |
PIDBCLK | Func | 0.032 | GPIO_GFCLK | |||
GPIO6 | GPIO6_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
GPIO6_DBCLK | Func | 0.032 | GPIO_GFCLK | FUNC_32K_CLK | OSC0 | |
PIDBCLK | Func | 0.032 | GPIO_GFCLK | |||
GPIO7 | GPIO7_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
GPIO7_DBCLK | Func | 0.032 | GPIO_GFCLK | FUNC_32K_CLK | OSC0 | |
PIDBCLK | Func | 0.032 | GPIO_GFCLK | |||
GPIO8 | GPIO8_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
GPIO8_DBCLK | Func | 0.032 | GPIO_GFCLK | FUNC_32K_CLK | OSC0 | |
PIDBCLK | Func | 0.032 | GPIO_GFCLK | |||
GPMC | GPMC_FCLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
GPU | GPU_FCLK1 | Func | GPU_CLK | GPU_CORE_GCLK | CORE_GPU_CLK | DPLL_CORE |
PER_GPU_CLK | DPLL_PER | |||||
GPU_GCLK | DPLL_GPU | |||||
GPU_FCLK2 | Func | GPU_CLK | GPU_HYD_GCLK | CORE_GPU_CLK | DPLL_CORE | |
PER_GPU_CLK | DPLL_PER | |||||
GPU_GCLK | DPLL_GPU | |||||
GPU_ICLK | Int | 266 | GPU_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
HDMI PHY | DSS_HDMI_PHY_CLK | Func | 38.4 | HDMI_PHY_GFCLK | FUNC_192M_CLK | DPLL_PER |
HDQ1W | HDQ1W_ICLK | Int & Func | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
HDQ1W_FCLK | Func | 12 | PER_12M_GFCLK | FUNC_192M_CLK | DPLL_PER | |
I2C1 | I2C1_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
I2C1_FCLK | Func | 96 | PER_96M_GFCLK | FUNC_192M_CLK | DPLL_PER | |
I2C2 | I2C2_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
I2C2_FCLK | Func | 96 | PER_96M_GFCLK | FUNC_192M_CLK | DPLL_PER | |
I2C3 | I2C3_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
I2C3_FCLK | Func | 96 | PER_96M_GFCLK | FUNC_192M_CLK | DPLL_PER | |
I2C4 | I2C4_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
I2C4_FCLK | Func | 96 | PER_96M_GFCLK | FUNC_192M_CLK | DPLL_PER | |
I2C5 | I2C5_ICLK | Int | 266 | IPU_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
I2C5_FCLK | Func | 96 | IPU_96M_GFCLK | FUNC_192M_CLK | DPLL_PER | |
IEEE1500_2_OCP | PI_L3CLK | Int & Func | 266 | L3INIT_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
IPU1 | IPU1_GFCLK | Int & Func | 425.6 | IPU1_GFCLK | DPLL_ABE_X2_CLK | DPLL_ABE |
CORE_IPU_ISS_BOOST_CLK | DPLL_CORE | |||||
IPU2 | IPU2_GFCLK | Int & Func | 425.6 | IPU2_GFCLK | CORE_IPU_ISS_BOOST_CLK | DPLL_CORE |
IVA | IVA_GCLK | Int | IVA_GCLK | IVA_GCLK | IVA_GFCLK | DPLL_IVA |
KBD | KBD_FCLK | Func | 0.032 | WKUPAON_SYS_GFCLK | WKUPAON_32K_GFCLK | OSC0 |
PICLKKBD | Func | 0.032 | WKUPAON_SYS_GFCLK | |||
KBD_ICLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 | |
PICLKOCP | Int | 38.4 | WKUPAON_GICLK | DPLL_ABE_X2_CLK | DPLL_ABE | |
L3_INSTR | L3_CLK | Int | L3_CLK | L3INSTR_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
L3_MAIN | L3_CLK1 | Int | L3_CLK | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
L3_CLK2 | Int | L3_CLK | L3INSTR_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
L4_CFG | L4_CFG_CLK | Int | 133 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
L4_PER1 | L4_PER1_CLK | Int | 133 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
L4_PER2 | L4_PER2_CLK | Int | 133 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
L4_PER3 | L4_PER3_CLK | Int | 133 | L4PER3_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
L4_WKUP | L4_WKUP_CLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
MAILBOX1 | MAILBOX1_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX2 | MAILBOX2_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX3 | MAILBOX3_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX4 | MAILBOX4_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX5 | MAILBOX5_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX6 | MAILBOX6_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX7 | MAILBOX7_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX8 | MAILBOX8_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX9 | MAILBOX9_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX10 | MAILBOX10_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX11 | MAILBOX11_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX12 | MAILBOX12_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MAILBOX13 | MAILBOX13_FLCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
McASP1 | MCASP1_AHCLKR | Func | 100 | MCASP1_AHCLKR | ABE_24M_GFCLK | DPLL_ABE |
ABE_SYS_CLK | OSC0 | |||||
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK0 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK3 | Module ATL | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
MCASP1_AHCLKX | Func | 100 | MCASP1_AHCLKX | ABE_24M_GFCLK | DPLL_ABE | |
ABE_SYS_CLK | OSC0 | |||||
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK0 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK3 | Module ATL | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
MCASP1_FCLK | Func | 192 | MCASP1_AUX_GFCLK | PER_ABE_X1_GFCLK | DPLL_ABE | |
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
MCASP1_ICLK | Int | 266 | IPU_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
McASP2 | MCASP2_AHCLKR | Func | 100 | MCASP2_AHCLKR | ABE_24M_GFCLK | DPLL_ABE |
ABE_SYS_CLK | OSC0 | |||||
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK3 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK0 | Module ATL | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
MCASP2_AHCLKX | Func | 100 | MCASP2_AHCLKX | ABE_24M_GFCLK | DPLL_ABE | |
ABE_SYS_CLK | OSC0 | |||||
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK3 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK0 | Module ATL | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
MCASP2_FCLK | Func | 192 | MCASP2_AUX_GFCLK | PER_ABE_X1_GFCLK | DPLL_ABE | |
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
MCASP2_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
McASP3 | MCASP3_AHCLKX | Func | 100 | MCASP3_AHCLKX | ABE_24M_GFCLK | DPLL_ABE |
ABE_SYS_CLK | OSC0 | |||||
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK3 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK0 | Module ATL | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
MCASP3_FCLK | Func | 192 | MCASP3_AUX_GFCLK | PER_ABE_X1_GFCLK | DPLL_ABE | |
VIDEO1_CLK | DPLL_ABE | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
MCASP3_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
McASP4 | MCASP4_AHCLKX | Func | 100 | MCASP4_AHCLKX | ABE_24M_GFCLK | DPLL_ABE |
ABE_SYS_CLK | OSC0 | |||||
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK3 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK0 | Module ATL | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
MCASP4_FCLK | Func | 192 | MCASP4_AUX_GFCLK | PER_ABE_X1_GFCLK | DPLL_ABE | |
VIDEO1_CLK | DPLL_ABE | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
MCASP4_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
McASP5 | MCASP5_AHCLKX | Func | 100 | MCASP5_AHCLKX | ABE_24M_GFCLK | DPLL_ABE |
ABE_SYS_CLK | OSC0 | |||||
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK3 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK0 | Module ATL | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
MCASP5_FCLK | Func | 192 | MCASP5_AUX_GFCLK | PER_ABE_X1_GFCLK | DPLL_ABE | |
VIDEO1_CLK | DPLL_ABE | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
MCASP5_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
McASP6 | MCASP6_AHCLKX | Func | 100 | MCASP6_AHCLKX | ABE_24M_GFCLK | DPLL_ABE |
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK3 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK0 | Module ATL | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
ABE_SYS_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MCASP6_FCLK | Func | 192 | MCASP6_AUX_GFCLK | PER_ABE_X1_GFCLK | DPLL_ABE | |
VIDEO1_CLK | DPLL_ABE | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
MCASP6_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
McASP7 | MCASP7_AHCLKX | Func | 100 | MCASP7_AHCLKX | ABE_24M_GFCLK | DPLL_ABE |
ABE_SYS_CLK | OSC0 | |||||
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK3 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK0 | Module ATL | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
MCASP7_FCLK | Func | 192 | MCASP7_AUX_GFCLK | PER_ABE_X1_GFCLK | DPLL_ABE | |
VIDEO1_CLK | DPLL_ABE | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
MCASP7_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
McASP8 | MCASP8_AHCLKX | Func | 100 | MCASP8_AHCLKX | ABE_24M_GFCLK | DPLL_ABE |
ABE_SYS_CLK | OSC0 | |||||
FUNC_24M_GFCLK | DPLL_PER | |||||
ATL_CLK3 | Module ATL | |||||
ATL_CLK2 | Module ATL | |||||
ATL_CLK1 | Module ATL | |||||
ATL_CLK0 | Module ATL | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
MLB_CLK | Module MLB | |||||
MLBP_CLK | Module MLB | |||||
MCASP8_FCLK | Func | 192 | MCASP8_AUX_GFCLK | PER_ABE_X1_GFCLK | DPLL_ABE | |
VIDEO1_CLK | DPLL_ABE | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
MCASP8_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
McSPI1 | SPI1_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SPI1_FCLK | Func | 48 | PER_48M_GFCLK | PER_48M_GFCLK | DPLL_PER | |
McSPI2 | SPI2_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SPI2_FCLK | Func | 48 | PER_48M_GFCLK | PER_48M_GFCLK | DPLL_PER | |
McSPI3 | SPI3_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SPI3_FCLK | Func | 48 | PER_48M_GFCLK | PER_48M_GFCLK | DPLL_PER | |
McSPI4 | SPI4_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SPI4_FCLK | Func | 48 | PER_48M_GFCLK | PER_48M_GFCLK | DPLL_PER | |
MLB_SS | MLB_L3_ICLK | Int | 266 | MLB_SHB_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MLB_L4_ICLK | Int | 133 | MLB_SPB_L4_GICLK | CORE_X2_CLK | DPLL_CORE | |
MLB_FCLK | Func | 266 | MLB_SYS_L3_GFCLK | CORE_X2_CLK | DPLL_CORE | |
MMC1 | MMC1_CLK_32K | Func | 0.032 | L3INIT_32K_GFCLK | FUNC_32K_CLK | OSC0 |
MMC1_FCLK | Func | 192 | MMC1_GFCLK | FUNC_192M_CLK | DPLL_PER | |
128 | FUNC_256M_CLK | DPLL_PER | ||||
MMC1_ICLK1 | Int | 266 | L3INIT_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
MMC1_ICLK2 | Int | 133 | L3INIT_L4_GICLK | CORE_X2_CLK | DPLL_CORE | |
MMC2 | MMC2_CLK_32K | Func | 0.032 | L3INIT_32K_GFCLK | FUNC_32K_CLK | OSC0 |
MMC2_FCLK | Func | 192 | MMC2_GFCLK | FUNC_192M_CLK | DPLL_PER | |
128 | FUNC_256M_CLK | DPLL_PER | ||||
MMC2_ICLK1 | Int | 266 | L3INIT_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
MMC2_ICLK2 | Int | 133 | L3INIT_L4_GICLK | CORE_X2_CLK | DPLL_CORE | |
MMC3 | MMC3_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MMC3_CLK_32K | Func | 0.032 | L4PER_32K_GFCLK | FUNC_32K_CLK | OSC0 | |
MMC3_FCLK | Func | 48 | MMC3_GFCLK | FUNC_192M_CLK | DPLL_PER | |
192 | ||||||
MMC4 | MMC4_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MMC4_CLK_32K | Func | 0.032 | L4PER_32K_GFCLK | FUNC_32K_CLK | OSC0 | |
MMC4_FCLK | Func | 48 | MMC4_GFCLK | FUNC_192M_CLK | DPLL_PER | |
192 | ||||||
MMU_EDMA | MMU1_CLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MMU_PCIESS | MMU2_CLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
MPU | MPU_CLK | Int & Func | MPU_CLK | MPU_GCLK | MPU_GCLK | DPLL_MPU |
MPU_EMU_DBG | FCLK | Int | 38.4 | EMU_SYS_CLK | SYS_CLK1 | OSC0 |
MPU_GCLK | DPLL_MPU | |||||
OCMC_RAM1 | OCMC1_L3_CLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
OCMC_RAM2 | OCMC2_L3_CLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
OCMC_RAM3 | OCMC3_L3_CLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
OCMC_ROM | OCMC_L3_CLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
OCP_WP_NOC | PICLKOCPL3 | Int | 266 | L3INSTR_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
OCP2SCP1 | L4CFG1_ADAPTER_CLKIN | Int | 133 | L3INIT_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
OCP2SCP2 | L4CFG2_ADAPTER_CLKIN | Int | 133 | L4CFG_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
OCP2SCP3 | L4CFG3_ADAPTER_CLKIN | Int | 133 | L3INIT_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
PCIESS1 | PCIE1_PHY_WKUP_CLK | Func | 0.032 | PCIE_32K_GFCLK | FUNC_32K_CLK | OSC0 |
PCIe_SS1_FICLK | Int | 266 | PCIE_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
PCIEPHY_CLK | Func | 2500 | PCIE_PHY_GCLK | PCIE_PHY_GCLK | APLL_PCIE | |
PCIEPHY_CLK_DIV | Func | 1250 | PCIE_PHY_DIV_GCLK | PCIE_PHY_DIV_GCLK | APLL_PCIE | |
PCIE1_REF_CLKIN | Func | 34.3 | PCIE_REF_GFCLK | CORE_USB_OTG_SS_LFPS_TX_CLK | DPLL_CORE | |
PCIE1_PWR_CLK | Func | 38.4 | PCIE_SYS_GFCLK | SYS_CLK1 | OSC0 | |
PCIESS2 | PCIE2_PHY_WKUP_CLK | Func | 0.032 | PCIE_32K_GFCLK | FUNC_32K_CLK | OSC0 |
PCIe_SS2_FICLK | Func | 266 | PCIE_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
PCIEPHY_CLK | Func | 2500 | PCIE_PHY_GCLK | PCIE_PHY_GCLK | APLL_PCIE | |
PCIEPHY_CLK_DIV | Func | 1250 | PCIE_PHY_DIV_GCLK | PCIE_PHY_DIV_GCLK | APLL_PCIE | |
PCIE2_REF_CLKIN | Func | 34.3 | PCIE_REF_GFCLK | CORE_USB_OTG_SS_LFPS_TX_CLK | DPLL_CORE | |
PCIE2_PWR_CLK | Func | 38.4 | PCIE_SYS_GFCLK | SYS_CLK1 | OSC0 | |
PRCM_MPU | 32K_CLK | Func | 0.032 | FUNC_32K_CLK | SYS_CLK1/610 | OSC0 |
SYS_CLK | Func | 38.4 | WKUPAON_ICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
PWMSS1 | PWMSS1_GICLK | Int & Func | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
PWMSS2 | PWMSS2_GICLK | Int & Func | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
PWMSS3 | PWMSS3_GICLK | Int & Func | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
QSPI | QSPI_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
QSPI_FCLK | Func | 128 | QSPI_GFCLK | FUNC_256M_CLK | DPLL_PER | |
PER_QSPI_CLK | DPLL_PER | |||||
RNG | RNG_ICLK | Int | 266 | L4SEC_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SAR_ROM | PRCM_ROM_CLOCK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SATA | SATA_FICLK | Int | 266 | L3INIT_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SATA_PMALIVE_FCLK | Func | 48 | L3INIT_48M_GFCLK | FUNC_192M_CLK | DPLL_PER | |
REF_CLK | Func | 38 | SATA_REF_GFCLK | SYS_CLK1 | OSC0 | |
SDMA | SDMA_FCLK | Int & Func | 266 | DMA_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SHA2MD51 | SHAM_1_CLK | Int | 266 | L4SEC_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SHA2MD52 | SHAM_2_CLK | Int | 266 | L4SEC_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
SL2 | IVA_GCLK | Int | IVA_GCLK | IVA_GCLK | IVA_GFCLK | DPLL_IVA |
SMARTREFLEX_CORE | MCLK | Int | 133 | COREAON_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
SYSCLK | Func | 38.4 | WKUPAON_ICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
SMARTREFLEX_DSPEVE | MCLK | Int | 133 | COREAON_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
SYSCLK | Func | 38.4 | WKUPAON_ICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
SMARTREFLEX_GPU | MCLK | Int | 133 | COREAON_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
SYSCLK | Func | 38.4 | WKUPAON_ICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
SMARTREFLEX_IVAHD | MCLK | Int | 133 | COREAON_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
SYSCLK | Func | 38.4 | WKUPAON_ICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
SMARTREFLEX_MPU | MCLK | Int | 133 | COREAON_L4_GICLK | CORE_X2_CLK | DPLL_CORE |
SYSCLK | Func | 38.4 | WKUPAON_ICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
SPINLOCK | SPINLOCK_ICLK | Int | 266 | L4CFG_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER1 | TIMER1_ICLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
TIMER1_FCLK | Func | 100 | TIMER1_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER2 | TIMER2_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER2_FCLK | Func | 100 | TIMER2_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER3 | TIMER3_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER3_FCLK | Func | 100 | TIMER3_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER4 | TIMER4_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER4_FCLK | Func | 100 | TIMER4_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER5 | TIMER5_ICLK | Int | 266 | IPU_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER5_FCLK | Func | 100 | TIMER5_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
CLKOUTMUX[0] | CLKOUTMUX[0] | |||||
TIMER6 | TIMER6_ICLK | Int | 266 | IPU_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER6_FCLK | Func | 100 | TIMER6_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
CLKOUTMUX[0] | CLKOUTMUX[0] | |||||
TIMER7 | TIMER7_ICLK | Int | 266 | IPU_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER7_FCLK | Func | 100 | TIMER7_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
CLKOUTMUX[0] | CLKOUTMUX[0] | |||||
TIMER8 | TIMER8_ICLK | Int | 266 | IPU_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER8_FCLK | Func | 100 | TIMER8_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
CLKOUTMUX[0] | CLKOUTMUX[0] | |||||
TIMER9 | TIMER9_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER9_FCLK | Func | 100 | TIMER9_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER10 | TIMER10_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER10_FCLK | Func | 100 | TIMER10_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER11 | TIMER11_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER11_FCLK | Func | 100 | TIMER11_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER12 | TIMER12_ICLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
TIMER12_FCLK | Func | 0.032 | OSC_32K_CLK | RC_CLK | OSC0 | |
TIMER13 | TIMER13_ICLK | Int | 266 | L4PER3_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER13_FCLK | Func | 100 | TIMER13_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER14 | TIMER14_ICLK | Int | 266 | L4PER3_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER14_FCLK | Func | 100 | TIMER14_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER15 | TIMER15_ICLK | Int | 266 | L4PER3_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER15_FCLK | Func | 100 | TIMER15_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TIMER16 | TIMER16_ICLK | Int | 266 | L4PER3_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TIMER16_FCLK | Func | 100 | TIMER16_GFCLK | SYS_CLK1 | OSC0 | |
FUNC_32K_CLK | OSC0 | |||||
SYS_CLK2 | OSC1 | |||||
XREF_CLK0 | XREF_CLK0 | |||||
XREF_CLK1 | XREF_CLK1 | |||||
XREF_CLK2 | XREF_CLK2 | |||||
XREF_CLK3 | XREF_CLK3 | |||||
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
VIDEO1_CLK | DPLL_VIDEO1 | |||||
VIDEO2_CLK | DPLL_VIDEO2 | |||||
HDMI_CLK | DPLL_HDMI | |||||
TPCC | TPCC_GCLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TPTC1 | TPTC0_GCLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
TPTC2 | TPTC1_GCLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
UART1 | UART1_FCLK | Func | 48 | UART1_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART1_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
UART2 | UART2_FCLK | Func | 48 | UART2_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART2_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
UART3 | UART3_FCLK | Func | 48 | UART3_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART3_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
UART4 | UART4_FCLK | Func | 48 | UART4_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART4_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
UART5 | UART5_FCLK | Func | 48 | UART5_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART5_ICLK | Int | 266 | L4PER_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
UART6 | UART6_FCLK | Func | 48 | UART6_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART6_ICLK | Int | 266 | IPU_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
UART7 | UART7_FCLK | Func | 48 | UART7_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART7_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
UART8 | UART8_FCLK | Func | 48 | UART8_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART8_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
UART9 | UART9_FCLK | Func | 48 | UART9_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART9_ICLK | Int | 266 | L4PER2_L3_GICLK | CORE_X2_CLK | DPLL_CORE | |
UART10 | UART10_FCLK | Func | 48 | UART10_GFCLK | FUNC_192M_CLK | DPLL_PER |
UART10_ICLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 | |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
USB1 | USB1_MICLK | Int | 266 | L3INIT_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
USB3PHY_REF_CLK | Func | 34.3 | USB_LFPS_TX_GFCLK | CORE_USB_OTG_SS_LFPS_TX_CLK | DPLL_CORE | |
USB2PHY1_TREF_CLK | Func | 38.4 | USB_OTG_SS_REF_CLK | SYS_CLK1 | OSC0 | |
USB2PHY1_REF_CLK | Func | 960 | L3INIT_960M_GFCLK | L3INIT_960_GFCLK | DPLL_USB | |
USB2 | USB2_MICLK | Int | 266 | L3INIT_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
USB2PHY2_TREF_CLK | Func | 38.4 | USB_OTG_SS_REF_CLK | SYS_CLK1 | OSC0 | |
USB2PHY2_REF_CLK | Func | 960 | L3INIT_960M_GFCLK | L3INIT_960_GFCLK | DPLL_USB | |
USB3 | USB3_MICLK | Int | 266 | L3INIT_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
USB3PHY_PWRS_CLK | Func | 38.4 | USB_OTG_SS_REF_CLK | SYS_CLK1 | OSC0 | |
USB4 | USB4_MICLK | Int | 266 | L3INIT_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
DPLL_USBSS_REF_CLK | Func | 38.4 | USB_OTG_SS_REF_CLK | SYS_CLK1 | OSC0 | |
USB_PHY1_CORE | USB2PHY1_WKUP_CLK | Func | 0.032 | COREAON_32K_GFCLK | SYS_CLK1/610 | OSC0 |
USB_PHY2_CORE | USB2PHY2_WKUP_CLK | Func | 0.032 | COREAON_32K_GFCLK | SYS_CLK1/610 | OSC0 |
USB_PHY3_CORE | USB3PHY_WKUP_CLK | Func | 0.032 | COREAON_32K_GFCLK | SYS_CLK1/610 | OSC0 |
VCP1 | VCP1_CLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
VCP2 | VCP2_CLK | Int | 266 | L3MAIN1_L3_GICLK | CORE_X2_CLK | DPLL_CORE |
VIP1 | L3_CLK_PROC_CLK | Int & Func | 266 | VIP1_GCLK | CORE_X2_CLK | DPLL_CORE |
CORE_ISS_MAIN_CLK | DPLL_CORE | |||||
VIP2 | L3_CLK_PROC_CLK | Int & Func | 266 | VIP2_GCLK | CORE_X2_CLK | DPLL_CORE |
CORE_ISS_MAIN_CLK | DPLL_CORE | |||||
VPE | L3_CLK_PROC_CLK | Int & Func | 300 | VPE_GCLK | CORE_ISS_MAIN_CLK | DPLL_CORE |
VIDEO1_CLKOUT4 | DPLL_VIDEO1 | |||||
WD_TIMER1 | PIOCPCLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
PITIMERCLK | Func | 0.032 | OSC_32K_CLK | RC_CLK | OSC0 | |
WD_TIMER2 | WD_TIMER2_ICLK | Int | 38.4 | WKUPAON_GICLK | SYS_CLK1 | OSC0 |
DPLL_ABE_X2_CLK | DPLL_ABE | |||||
WD_TIMER2_FCLK | Func | 0.032 | WKUPAON_SYS_GFCLK | WKUPAON_32K_GFCLK | OSC0 |