SPRS993E March 2017 – December 2018 DRA76P , DRA77P
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. It works as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories.
General SPI features:
NOTE
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The IO Timings provided in this section are only valid for some QSPI usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section.
CAUTION
The IO Timings provided in this section are only valid when all QSPI Chip Selects used in a system are configured to use the same Clock Mode (either Clock Mode 0 or Clock Mode3).
Table 5-72 and Table 5-73 present timing and switching characteristics for Quad SPI interface.
No | PARAMETER | DESCRIPTION | Mode | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
Q1 | tc(SCLK) | Cycle time, sclk | Manual IO Timing Modes, Clock Mode 0 | 10.41 | ns | |
Manual IO Timing Modes, Clock Mode 3 | 13.02 | ns | ||||
Bootmode, Clock Mode 3 | 20.8 | |||||
Q2 | tw(SCLKL) | Pulse duration, sclk low | All | Y×P-1 (1) | ns | |
Q3 | tw(SCLKH) | Pulse duration, sclk high | All | Y×P-1 (1) | ns | |
Q4 | td(CS-SCLK) | Delay time, sclk falling edge to cs active edge, CS3:0 | Manual IO Timing Modes | -M×P-1 (2)(3) | -M×P+2 (2)(3) | ns |
Bootmode | -M×P-2.5 (2)(3) | -M×P+2.5 (2)(3) | ||||
Q5 | td(SCLK-CS) | Delay time, sclk falling edge to cs inactive edge, CS3:0 | Manual IO Timing Modes | N×P-1 (2)(3) | N×P+2 (2)(3) | ns |
Bootmode | N×P-2.5 (2)(3) | N×P+2.5 (2)(3) | ||||
Q6 | td(SCLK-D1) | Delay time, sclk falling edge to d[0] transition | Manual IO Timing Modes | -1 | 2 | ns |
Bootmode | -2.5 | 2.5 | ||||
Q7 | tena(CS-D1LZ) | Enable time, cs active edge to d[0] driven (lo-z) | All | -P-3.5 | -P+2.5 | ns |
Q8 | tdis(CS-D1Z) | Disable time, cs active edge to d[0] tri-stated (hi-z) | All | -P-2.5 | -P+2.0 | ns |
Q9 | td(SCLK-D0) | Delay time, sclk first falling edge to first d[0] transition | Manual IO Timing Modes, PHA=0 Only | -1-P | 2-P | ns |
Bootmode, PHA=0 Only | -2.5-P | 2.5-P |
CAUTION
The IO Timings provided in this section are only valid for some QSPI usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section.
No | PARAMETER | DESCRIPTION | Mode | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
Q12 | tsu(D-RTCLK) | Setup time, d[3:0] valid before falling rtclk edge | Manual IO Timing Modes, Clock Mode 0 | 2.9 | ns | |
tsu(D-SCLK) | Setup time, d[3:0] valid before falling sclk edge | Manual IO Timing Modes, Clock Mode 3 | 5.7 | ns | ||
Boot Mode, Clock Mode 3 | 12.3 | ns | ||||
Q13 | th(RTCLK-D) | Hold time, d[3:0] valid after falling rtclk edge | Manual IO Timing Mode, Clock Mode 0 | -0.1 | ns | |
th(SCLK-D) | Hold time, d[3:0] valid after falling sclk edge | Manual IO Timing Mode, Clock Mode 3 | 0.1 | ns | ||
Boot Mode, Clock Mode 3 | 0.1 | ns | ||||
Q14 | tsu(D-SCLK) | Setup time, final d[3:0] bit valid before final falling sclk edge | Manual IO Timing Mode, Clock Mode 3 | 5.7-P (1) | ns | |
Boot Mode, Clock Mode 3 | 12.3-P (1) | ns | ||||
Q15 | th(SCLK-D) | Hold time, final d[3:0] bit valid after final falling sclk edge | Manual IO Timing Mode, Clock Mode 3 | 0.1+P (1) | ns | |
Boot Mode, Clock Mode 3 | 0.1+P (1) | ns |
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more information, see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for QSPI. See Table 5-29, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-74, Manual Functions Mapping for QSPI for a definition of the Manual modes.
Table 5-74 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | QSPI_MODE0_MANUAL1 | QSPI_MODE3_MANUAL1 | CFG REGISTER | MUXMODE | ||
---|---|---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | A_DELAY (ps) | G_DELAY (ps) | 1 | |||
R2 | gpmc_a13 | 0 | 0 | 0 | 0 | CFG_GPMC_A13_IN | qspi1_rtclk |
R6 | gpmc_a14 | 2149 | 1052 | 0 | 0 | CFG_GPMC_A14_IN | qspi1_d3 |
T2 | gpmc_a15 | 2121 | 997 | 0 | 0 | CFG_GPMC_A15_IN | qspi1_d2 |
U1 | gpmc_a16 | 2159 | 1134 | 0 | 0 | CFG_GPMC_A16_IN | qspi1_d0 |
U1 | gpmc_a16 | 0 | 0 | 0 | 0 | CFG_GPMC_A16_OUT | qspi1_d0 |
P3 | gpmc_a17 | 2135 | 1085 | 0 | 0 | CFG_GPMC_A17_IN | qspi1_d1 |
R1 | gpmc_a18 | 0 | 0 | 151 | 0 | CFG_GPMC_A18_OUT | qspi1_sclk |
R5 | gpmc_a3 | 0 | 0 | 0 | 0 | CFG_GPMC_A3_OUT | qspi1_cs2 |
M6 | gpmc_a4 | 0 | 0 | 0 | 0 | CFG_GPMC_A4_OUT | qspi1_cs3 |
P2 | gpmc_cs2 | 0 | 0 | 0 | 0 | CFG_GPMC_CS2_OUT | qspi1_cs0 |
P1 | gpmc_cs3 | 0 | 0 | 22 | 0 | CFG_GPMC_CS3_OUT | qspi1_cs1 |