SPRS993E March   2017  – December 2018 DRA76P , DRA77P

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
    2. 3.2 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 SATA
      16. 4.3.16 PCIe
      17. 4.3.17 DCAN and MCAN
      18. 4.3.18 GMAC_SW
      19. 4.3.19 MLB
      20. 4.3.20 eMMC/SD/SDIO
      21. 4.3.21 GPIO
      22. 4.3.22 KBD
      23. 4.3.23 PWM
      24. 4.3.24 ATL
      25. 4.3.25 Test Interfaces
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 PRCM
        3. 4.3.26.3 SDMA
        4. 4.3.26.4 INTC
        5. 4.3.26.5 Observability
        6. 4.3.26.6 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  LVCMOS CSI2 DC Electrical Characteristics
      5. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      HDMIPHY DC Electrical Characteristics
      10. 5.7.2      USBPHY DC Electrical Characteristics
      11. 5.7.3      SATAPHY DC Electrical Characteristics
      12. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
          3. 5.10.4.4.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  Timers
        9. 5.10.6.9  I2C
          1. Table 5-60 Timing Requirements for I2C Input Timings
          2. Table 5-61 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-62 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        10. 5.10.6.10 HDQ1W
          1. 5.10.6.10.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.10.2 HDQ/1-Wire—1-Wire Mode
        11. 5.10.6.11 UART
          1. Table 5-67 Timing Requirements for UART
          2. Table 5-68 Switching Characteristics Over Recommended Operating Conditions for UART
        12. 5.10.6.12 McSPI
        13. 5.10.6.13 QSPI
        14. 5.10.6.14 McASP
          1. Table 5-75 Timing Requirements for McASP1
          2. Table 5-76 Timing Requirements for McASP2
          3. Table 5-77 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-78 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-79 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-80 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        15. 5.10.6.15 USB
          1. 5.10.6.15.1 USB1 DRD PHY
          2. 5.10.6.15.2 USB2 PHY
          3. 5.10.6.15.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
        16. 5.10.6.16 SATA
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 CAN
          1. 5.10.6.18.1 DCAN
          2. 5.10.6.18.2 MCAN-FD
          3. Table 5-95  Timing Requirements for CANx Receive
          4. Table 5-96  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-97  Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-98  Timing Requirements for miin_txclk - MII Operation
            3. Table 5-99  Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-100 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-105 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-106 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-107 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-108 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-112 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-113 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-114 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-115 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit Data, SDR, Half-Cycle
            2. 5.10.6.21.1.2 High-Speed, 4-bit Data, SDR, Half-Cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit Data, Half-Cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit Data, Half-Cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit Data, Half-Cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit Data, Half-Cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit Data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit Data, Half Cycle
            2. 5.10.6.21.2.2 High-Speed JC64 SDR, 8-bit Data, Half Cycle
            3. 5.10.6.21.2.3 High-Speed HS200 JC64 SDR, 8-bit Data, Half Cycle
            4. 5.10.6.21.2.4 High-Speed JC64 DDR, 8-bit Data
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High-Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 ATL
          1. 5.10.6.23.1 ATL Electrical Data/Timing
            1. Table 5-171 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
        24. 5.10.6.24 System and Miscellaneous Interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-172 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-173 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-174 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-175 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  ISS
    6. 6.6  IVA
    7. 6.7  EVE
    8. 6.8  IPU
    9. 6.9  VPE
    10. 6.10 GPU
    11. 6.11 ATL Overview
    12. 6.12 Memory Subsystem
      1. 6.12.1 EMIF
      2. 6.12.2 GPMC
      3. 6.12.3 ELM
      4. 6.12.4 OCMC
    13. 6.13 Interprocessor Communication
      1. 6.13.1 Mailbox
      2. 6.13.2 Spinlock
    14. 6.14 Interrupt Controller
    15. 6.15 EDMA
    16. 6.16 Peripherals
      1. 6.16.1  VIP
      2. 6.16.2  DSS
      3. 6.16.3  Timers
      4. 6.16.4  I2C
      5. 6.16.5  HDQ1W
      6. 6.16.6  UART
        1. 6.16.6.1 UART Features
        2. 6.16.6.2 IrDA Features
        3. 6.16.6.3 CIR Features
      7. 6.16.7  McSPI
      8. 6.16.8  QSPI
      9. 6.16.9  McASP
      10. 6.16.10 USB
      11. 6.16.11 SATA
      12. 6.16.12 PCIe
      13. 6.16.13 CAN
      14. 6.16.14 GMAC_SW
      15. 6.16.15 MLB
      16. 6.16.16 CSI2
        1. 6.16.16.1 CSI-2 MIPI D-PHY
      17. 6.16.17 eMMC/SD/SDIO
      18. 6.16.18 GPIO
      19. 6.16.19 ePWM
      20. 6.16.20 eCAP
      21. 6.16.21 eQEP
    17. 6.17 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_mpu Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 JTAG Interface
            11. 7.5.2.2.2.11 Power Regulators
        3. 7.5.2.3 Electrostatic Discharge (ESD)
          1. 7.5.2.3.1 IEC ESD Stressing Test
            1. 7.5.2.3.1.1 Test Mode
            2. 7.5.2.3.1.2 Air Discharge Mode
            3. 7.5.2.3.1.3 Test Type
          2. 7.5.2.3.2 TI Component Level IEC ESD Test
          3. 7.5.2.3.3 Construction of a Custom USB Connector
          4. 7.5.2.3.4 ESD Protection System Design Consideration
        4. 7.5.2.4 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 SATA Board Design and Layout Guidelines
        1. 7.5.5.1 SATA Interface Schematic
        2. 7.5.5.2 Compatible SATA Components and Modes
        3. 7.5.5.3 PCB Stackup Specifications
        4. 7.5.5.4 Routing Specifications
      6. 7.5.6 PCIe Board Design and Layout Guidelines
        1. 7.5.6.1 PCIe Connections and Interface Compliance
          1. 7.5.6.1.1 Coupling Capacitors
          2. 7.5.6.1.2 Polarity Inversion
        2. 7.5.6.2 Non-standard PCIe connections
          1. 7.5.6.2.1 PCB Stackup Specifications
          2. 7.5.6.2.2 Routing Specifications
            1. 7.5.6.2.2.1 Impedance
            2. 7.5.6.2.2.2 Differential Coupling
            3. 7.5.6.2.2.3 Pair Length Matching
        3. 7.5.6.3 LJCB_REFN/P Connections
      7. 7.5.7 CSI2 Board Design and Routing Guidelines
        1. 7.5.7.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.7.1.1 General Guidelines
          2. 7.5.7.1.2 Length Mismatch Guidelines
            1. 7.5.7.1.2.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.7.1.3 Frequency-domain Specification Guidelines
    6. 7.6 DDR2/DDR3 Board Design and Layout Guidelines
      1. 7.6.1 DDR2/DDR3 General Board Layout Guidelines
      2. 7.6.2 DDR2 Board Design and Layout Guidelines
        1. 7.6.2.1 Board Designs
        2. 7.6.2.2 DDR2 Interface
          1. 7.6.2.2.1  DDR2 Interface Schematic
          2. 7.6.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.6.2.2.3  PCB Stackup
          4. 7.6.2.2.4  Placement
          5. 7.6.2.2.5  DDR2 Keepout Region
          6. 7.6.2.2.6  Bulk Bypass Capacitors
          7. 7.6.2.2.7  High-Speed Bypass Capacitors
          8. 7.6.2.2.8  Net Classes
          9. 7.6.2.2.9  DDR2 Signal Termination
          10. 7.6.2.2.10 VREF Routing
        3. 7.6.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 7.6.3 DDR3 Board Design and Layout Guidelines
        1. 7.6.3.1  Board Designs
        2. 7.6.3.2  DDR3 EMIF
        3. 7.6.3.3  DDR3 Device Combinations
        4. 7.6.3.4  DDR3 Interface Schematic
          1. 7.6.3.4.1 32-Bit DDR3 Interface
          2. 7.6.3.4.2 16-Bit DDR3 Interface
        5. 7.6.3.5  Compatible JEDEC DDR3 Devices
        6. 7.6.3.6  PCB Stackup
        7. 7.6.3.7  Placement
        8. 7.6.3.8  DDR3 Keepout Region
        9. 7.6.3.9  Bulk Bypass Capacitors
        10. 7.6.3.10 High-Speed Bypass Capacitors
          1. 7.6.3.10.1 Return Current Bypass Capacitors
        11. 7.6.3.11 Net Classes
        12. 7.6.3.12 DDR3 Signal Termination
        13. 7.6.3.13 VREF_DDR Routing
        14. 7.6.3.14 VTT
        15. 7.6.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.6.3.15.1 Four DDR3 Devices
            1. 7.6.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.6.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.6.3.15.2 Two DDR3 Devices
            1. 7.6.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.6.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.6.3.15.3 One DDR3 Device
            1. 7.6.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.6.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.6.3.16 Data Topologies and Routing Definition
          1. 7.6.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.6.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.6.3.17 Routing Specification
          1. 7.6.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.6.3.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1  Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2  Tools and Software
    3. 8.3  Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4  Receiving Notification of Documentation Updates
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ACD|784
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-115 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps (1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
RGMII5 tosu(TXD-TXC) Output Setup time, transmit selected signals valid to rgmiin_txc high/low RGMII0, Internal Delay Enabled, 1000 Mbps 1.05 (2) ns
RGMII0, Internal Delay Enabled, 10/100 Mbps 1.2 ns
RGMII1, Internal Delay Enabled, 1000 Mbps 1.05(3) ns
RGMII1, Internal Delay Enabled, 10/100 Mbps 1.2 ns
RGMII6 toh(TXC-TXD) Output Hold time, transmit selected signals valid after rgmiin_txc high/low RGMII0, Internal Delay Enabled, 1000 Mbps 1.05 (2) ns
RGMII0, Internal Delay Enabled, 10/100 Mbps 1.2 ns
RGMII1, Internal Delay Enabled, 1000 Mbps 1.05 (3) ns
RGMII1, Internal Delay Enabled, 10/100 Mbps 1.2 ns
  1. For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
  2. RGMII0 1000Mbps operation requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched within 50pS of rgmii0_txc.
  3. RGMII1 1000Mbps operation requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched within 50pS of rgmii1_txc.
DRA77P DRA76P SPRS8xx_GMAC_RGMIITX_09.gif
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
Figure 5-76 GMAC Transmit Interface Timing RGMIIn Operation

In Table 5-116 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.

Table 5-116 GMAC RGMII IOSETs

SIGNALS IOSET3 IOSET4
BALL MUX BALL MUX
GMAC RGMII1
rgmii1_txd3 C2 3
rgmii1_txd2 C3 3
rgmii1_txd1 B2 3
rgmii1_txd0 B5 3
rgmii1_rxd3 B3 3
rgmii1_rxd2 B4 3
rgmii1_rxd1 C4 3
rgmii1_rxd0 A4 3
rgmii1_rxctl A3 3
rgmii1_txc E6 3
rgmii1_txctl C1 3
rgmii1_rxc D4 3
GMAC RGMII0
rgmii0_txd3 T4 0
rgmii0_txd2 T3 0
rgmii0_txd1 U6 0
rgmii0_txd0 T5 0
rgmii0_rxd3 W2 0
rgmii0_rxd2 V3 0
rgmii0_rxd1 Y2 0
rgmii0_rxd0 W1 0
rgmii0_txc T6 0
rgmii0_rxctl V4 0
rgmii0_rxc U4 0
rgmii0_txctl U5 0

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to guarantee some IO timings for GMAC. See Table 5-29, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-117, Manual Functions Mapping for GMAC RGMII0 for a definition of the Manual modes.

Table 5-118 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-117 Manual Functions Mapping for GMAC RGMII0

BALL BALL NAME GMAC_RGMII0_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 0
U4 rgmii0_rxc 451 0 CFG_RGMII0_RXC_IN rgmii0_rxc
V4 rgmii0_rxctl 127 1571 CFG_RGMII0_RXCTL_IN rgmii0_rxctl
W1 rgmii0_rxd0 165 1178 CFG_RGMII0_RXD0_IN rgmii0_rxd0
Y2 rgmii0_rxd1 136 1302 CFG_RGMII0_RXD1_IN rgmii0_rxd1
V3 rgmii0_rxd2 0 1520 CFG_RGMII0_RXD2_IN rgmii0_rxd2
W2 rgmii0_rxd3 28 1690 CFG_RGMII0_RXD3_IN rgmii0_rxd3
T6 rgmii0_txc 121 0 CFG_RGMII0_TXC_OUT rgmii0_txc
U5 rgmii0_txctl 410 0 CFG_RGMII0_TXCTL_OUT rgmii0_txctl
T5 rgmii0_txd0 483 0 CFG_RGMII0_TXD0_OUT rgmii0_txd0
U6 rgmii0_txd1 335 0 CFG_RGMII0_TXD1_OUT rgmii0_txd1
T3 rgmii0_txd2 330 0 CFG_RGMII0_TXD2_OUT rgmii0_txd2
T4 rgmii0_txd3 522 0 CFG_RGMII0_TXD3_OUT rgmii0_txd3

Manual IO Timings Modes must be used to guarantee some IO timings for GMAC. See Table 5-29, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-118, Manual Functions Mapping for GMAC RGMII1 for a definition of the Manual modes.

Table 5-118 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-118 Manual Functions Mapping for GMAC RGMII1

BALL BALL NAME GMAC_RGMII1_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 3
D4 vin2a_d18 417 0 CFG_VIN2A_D18_IN rgmii1_rxc
A3 vin2a_d19 156 843 CFG_VIN2A_D19_IN rgmii1_rxctl
B3 vin2a_d20 223 1413 CFG_VIN2A_D20_IN rgmii1_rxd3
B4 vin2a_d21 169 1415 CFG_VIN2A_D21_IN rgmii1_rxd2
C4 vin2a_d22 43 1150 CFG_VIN2A_D22_IN rgmii1_rxd1
A4 vin2a_d23 0 1210 CFG_VIN2A_D23_IN rgmii1_rxd0
E6 vin2a_d12 147 0 CFG_VIN2A_D12_OUT rgmii1_txc
C1 vin2a_d13 480 0 CFG_VIN2A_D13_OUT rgmii1_txctl
C2 vin2a_d14 378 0 CFG_VIN2A_D14_OUT rgmii1_txd3
C3 vin2a_d15 562 0 CFG_VIN2A_D15_OUT rgmii1_txd2
B2 vin2a_d16 483 0 CFG_VIN2A_D16_OUT rgmii1_txd1
B5 vin2a_d17 380 0 CFG_VIN2A_D17_OUT rgmii1_txd0