SPRS993E March 2017 – December 2018 DRA76P , DRA77P
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Some general routing guidelines regarding USB 3.0:
Table 7-11 and Table 7-12 present routing specification and recommendations for USB1 in the device.
PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|
Device balls to USB 3.0 connector trace length | 3500 | Mils | ||
Skew within a differential pair | 3 | 6 | Mils | |
Number of stubs allowed on TX/RX traces | 0 | Stubs | ||
TX/RX pair differential impedance | 83 | 90 | 97 | Ω |
Number of vias on each TX/RX trace(1) | 2 | Vias | ||
Differential pair to any other trace spacing (2)(3)(4) | 2xDS | 3xDS | ||
Number of ground plane cuts allowed within USB3 routing region (except for specific ground carving as explained in this document) | 0 | Cuts | ||
Number of layers between USB3.0 routing region and reference ground plane | 0 | Layers | ||
PCB trace width | 6 | Mils | ||
PCB BGA escape via pad size | 18 | Mils | ||
PCB BGA escape via hole size | 10 | Mils |
Item | Description | Reason |
---|---|---|
ESD location | Place ESD component on same layer as connector (no via or stub to ESD component) | Eliminate reflection loss from via and stub to ESD |
ESD part number | TPD1E05U06 | Minimize capacitance (0.42pF) |
CMF part number | DLW21SN900HQ2 | Manufacturer’s recommended device |
Connector | Use USB3.0 connector with supporting s-parameter model | Enable full signal chain simulation |
Carve Ground | Carve GND underneath AC Caps, ESD, CMF, and connector | Minimize capacitance under ESD and CMF |
Round pads | Minimize pad size and round the corners of the pads for the ESD and CMF components | Minimize capacitance |
Vias | Max 2 vias per signal trace. If vias are required, place vias close to the AC Caps and CMFs. Vias under the SoC grid array may be used if necessary to route signals away from BGA pattern. | Vias significantly degrade signal integrity at 2.5GHz |
Figure 7-41 presents an example layout, demonstrating the “carve GND” concept.