SPRS975 Data sheet

SPRS975H August 2016 – February 2020 DRA780 , DRA781 , DRA782 , DRA783 , DRA785 , DRA786 , DRA787 , DRA788

PRODUCTION DATA.

Refer to the PDF data sheet for device specific package drawings

Table 5-37 and Table 5-38 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-34, Figure 5-35, Figure 5-36 and Figure 5-37).

NO.	PARAMETER	DESCRIPTION	MIN	MAX	UNIT
GNF12	t_acc(DAT)	Data maximum access time (GPMC_FCLK Cycles)		J	cycles
-	t_su(DV-OEH)	Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high	1.9		ns
-	-	t_h(OEH-DV)	Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high	1		ns

NO.	PARAMETER	DESCRIPTION	MIN	MAX	UNIT
-	t_r(DO)	Rising time, gpmc_ad[15:0] output data	0.447	4.067	ns
-	-	t_f(DO)	Fallling time, gpmc_ad[15:0] output data	0.43	4.463	ns
GNF0	t_w(nWEV)	Pulse duration, gpmc_wen valid time		A ^⁽¹⁾	ns
GNF1	t_d(nCSV-nWEV)	Delay time, gpmc_cs[7:0] valid to gpmc_wen valid	B - 0.2 ^⁽²⁾	B + 2.0 ^⁽²⁾	ns
GNF2	t_d(CLEH-nWEV)	Delay time, gpmc_ben[1:0] high to gpmc_wen valid	C - 0.2 ^⁽³⁾	C + 2.0 ^⁽³⁾	ns
GNF3	t_d(nWEV-DV)	Delay time, gpmc_ad[15:0] valid to gpmc_wen valid	D - 0.2 ^⁽⁴⁾	D + 2.0 ^⁽⁴⁾	ns
GNF4	t_d(nWEIV-DIV)	Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid	E - 0.2 ^⁽⁵⁾	E + 2.0 ^⁽⁵⁾	ns
GNF5	t_{d(nWEIV-CLEIV)}	Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid	F - 0.2 ^⁽⁶⁾	F + 2.0 ^⁽⁶⁾	ns
GNF6	t_{d(nWEIV-nCSIV)}	Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid	G - 0.2 ^⁽⁷⁾	G + 2.0 ^⁽⁷⁾	ns
GNF7	t_d(ALEH-nWEV)	Delay time, gpmc_advn_ale high to gpmc_wen valid	C - 0.2 ^⁽³⁾	C + 2.0 ^⁽³⁾	ns
GNF8	t_{d(nWEIV-ALEIV)}	Delay time, gpmc_wen invalid to gpmc_advn_ale invalid	F - 0.2 ^⁽⁶⁾	F + 2.0 ^⁽⁶⁾	ns
GNF9	t_c(nWE)	Cycle time, write cycle time		H ^⁽⁸⁾	ns
GNF10	t_d(nCSV-nOEV)	Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid	I - 0.2 ^⁽⁹⁾	I + 2.0 ^⁽⁹⁾	ns
GNF13	t_w(nOEV)	Pulse duration, gpmc_oen_ren valid time		K	ns
GNF14	t_c(nOE)	Cycle time, read cycle time		L ^⁽¹⁰⁾	ns
GNF15	t_{d(nOEIV-nCSIV)}	Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid	M - 0.2 ^⁽¹¹⁾	M + 2.0 ^⁽¹¹⁾	ns

A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK
C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK
D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay ) × GPMC_FCLK
E = (WrCycleTime – WEOffTime × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay ) × GPMC_FCLK
F = (ADVWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay ) × GPMC_FCLK
G = (CSWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay ) × GPMC_FCLK
H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK
I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK
K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK
L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK
M = (CSRdOffTime – OEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay ) × GPMC_FCLK

Figure 5-34 GPMC / NAND Flash - Command Latch Cycle Timing^⁽¹⁾

Figure 5-35 GPMC / NAND Flash - Address Latch Cycle Timing^⁽¹⁾

Figure 5-36 GPMC / NAND Flash - Data Read Cycle Timing^{⁽¹⁾⁽²⁾⁽³⁾}

GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.

Figure 5-37 GPMC / NAND Flash - Data Write Cycle Timing^⁽¹⁾

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bit field for each corresponding pad control register.

The pad control registers are presented Table 4-29 and described in Device TRM, Control Module section.