SPRS975 Data sheet

SPRS975H August 2016 – February 2020 DRA780 , DRA781 , DRA782 , DRA783 , DRA785 , DRA786 , DRA787 , DRA788

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ABF|367

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprs975h_oa

7.7.2.2.7 High Speed Bypass Capacitors

TI recommends that a PDN/power integrity analysis is performed to ensure that capacitor selection and placement is optimal for a given implementation. This section provides guidelines that can serve as a good starting point.

High speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power, and processor/DDR ground connections. Table 7-16 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:

Fit as many HS bypass capacitors as possible.
HS bypass capacitor value is < 1µF
Minimize the distance from the bypass cap to the pins/balls being bypassed.
Use the smallest physical sized capacitors possible with the highest capacitance readily available.
Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest hole size via possible.
Minimize via sharing. Note the limites on via sharing shown in Table 7-16.

Table 7-16 High Speed Bypass Capacitors

NO.	PARAMETER	MIN	TYP	MAX	UNIT
HS21	HS bypass capacitor package size^⁽¹⁾		0201	0402	10 Mils
HS22	Distance, HS bypass capacitor to processor being bypassed^{⁽²⁾⁽³⁾⁽⁴⁾}			400^⁽¹²⁾	Mils
HS23	Processor HS bypass capacitor count ^⁽¹²⁾		12^⁽¹¹⁾		Devices
HS24	Processor HS bypass capacitor total capacitance per vdds_ddrx rail ^⁽¹²⁾		3.4		μF
HS25	Number of connection vias for each device power/ground ball per vdds_ddrx rail^⁽⁵⁾	1			Vias
HS26	Trace length from device power/ground ball to connection via^⁽²⁾		35	70	Mils
HS27	Distance, HS bypass capacitor to DDR device being bypassed^⁽⁶⁾			150	Mils
HS28	Number of connection vias for each HS capacitor^{⁽⁸⁾⁽⁹⁾}		4 ^⁽¹⁴⁾		Vias
HS29	DDR2 device HS bypass capacitor count^⁽⁷⁾		12 ^⁽¹³⁾		Devices
HS210	DDR2 device HS bypass capacitor total capacitance^⁽⁷⁾	0.85			μF
HS211	Trace length from bypass capacitor connect to connection via^{⁽²⁾⁽⁹⁾}		35	100	Mils
HS212	Number of connection vias for each DDR2 device power/ground ball^⁽¹⁰⁾	1			Vias
HS213	Trace length from DDR2 device power/ground ball to connection via^{⁽²⁾⁽⁸⁾}		35	60	Mils

LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
Closer/shorter is better.
Measured from the nearest processor power/ground ball to the center of the capacitor package.
Three of these capacitors should be located underneath the processor, between the cluster of vdds_ddrx balls and ground balls, between the DDR interfaces on the package.
See the Via Channel™ escape for the processor package.
Measured from the DDR2 device power/ground ball to the center of the capacitor package.
Per DDR2 device.
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board.
An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
Up to a total of two pairs of DDR power/ground balls may share a via.
The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
For more information, see Section 7.3, Core Power Domains
For more information refer to DDR2 specification.
Preferred configuration is 4 vias: 2 to power and 2 to ground.