SPRS975H August 2016 – February 2020 DRA780 , DRA781 , DRA782 , DRA783 , DRA785 , DRA786 , DRA787 , DRA788
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Figure 5-54, Figure 5-55, Table 5-67, and Table 5-68 present Timing requirements and Switching characteristics for MMC - SD and SDIO Default speed in receiver and transmiter mode.
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
DS5 | tsu(cmdV-clkH) | Setup time, mmc_cmd valid before mmc_clk rising clock edge | 5.11 | ns | |
DS6 | th(clkH-cmdV) | Hold time, mmc_cmd valid after mmc_clk rising clock edge | 20.46 | ns | |
DS7 | tsu(dV-clkH) | Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge | 5.11 | ns | |
DS8 | th(clkH-dV) | Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge | 20.46 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
DS0 | fop(clk) | Operating frequency, mmc_clk | 24 | MHz | |
DS1 | tw(clkH) | Pulse duration, mmc_clk high | 0.5×P-0.270 | ns | |
DS2 | tw(clkL) | Pulse duration, mmc_clk low | 0.5×P-0.270 | ns | |
DS3 | td(clkL-cmdV) | Delay time, mmc_clk falling clock edge to mmc_cmd transition | -14.93 | 14.93 | ns |
DS4 | td(clkL-dV) | Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition | -14.93 | 14.93 | ns |