SPRS975H August 2016 – February 2020 DRA780 , DRA781 , DRA782 , DRA783 , DRA785 , DRA786 , DRA787 , DRA788
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Figure 5-60, Figure 5-61, Table 5-73, and Table 5-74 present Timing requirements and Switching characteristics for MMC - SD and SDIO SDR25 in receiver and transmiter mode.
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SDR253 | tsu(cmdV-clkH) | Setup time, mmc_cmd valid before mmc_clk rising clock edge | 5.3 | ns | |
SDR254 | th(clkH-cmdV) | Hold time, mmc_cmd valid after mmc_clk rising clock edge | 1.6 | ns | |
SDR257 | tsu(dV-clkH) | Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge | 5.3 | ns | |
SDR258 | th(clkH-dV) | Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge | 1.6 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SDR251 | fop(clk) | Operating frequency, mmc_clk | 48 | MHz | |
SDR252H | tw(clkH) | Pulse duration, mmc_clk high | 0.5×P-0.270 | ns | |
SDR252L | tw(clkL) | Pulse duration, mmc_clk low | 0.5×P-0.270 | ns | |
SDR255 | td(clkL-cmdV) | Delay time, mmc_clk falling clock edge to mmc_cmd transition | -8.8 | 6.6 | ns |
SDR256 | td(clkL-dV) | Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition | -8.8 | 6.6 | ns |
CAUTION
The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-75.
In Table 5-75 are presented the specific groupings of signals (IOSET) for use with MMC.