JAJSFR8 データシート

SPRS968F August 2016 – November 2019 DRA790 , DRA791 , DRA793 , DRA797

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

CBD|538

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprs968f_oa

5.10.6.4 DSS

Two Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 2 and DPI Video Output 3.

NOTE

The DPI Video Output i (i = 2, 3) interface is also referred to as VOUTi.

Every VOUT interface consists of:

24-bit data bus (data[23:0])
Horizontal synchronization signal (HSYNC)
Vertical synchronization signal (VSYNC)
Data enable (DE)
Field ID (FID)
Pixel clock (CLK)

NOTE

For more information, see the Display Subsystem chapter of the Device TRM.

CAUTION

The I/O Timings provided in this section are valid only if signals within a single IOSET are used. The IOSETs are defined in Table 5-43.

CAUTION

The I/O Timings provided in this section are valid only for some DSS usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

CAUTION

All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).

Table 5-39, Table 5-40 through Table 5-42 assume testing over the recommended operating conditions and electrical characteristic conditions.

Table 5-39 DPI Video Output i (i = 2, 3) Default Switching Characteristics^{⁽¹⁾⁽²⁾}

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
D1	t_c(clk)	Cycle time, output pixel clock vouti_clk	DPI2/3	11.76		ns
D2	t_w(clkL)	Pulse duration, output pixel clock vouti_clk low		P × 0.5-1 ^⁽¹⁾		ns
D3	t_w(clkH)	Pulse duration, output pixel clock vouti_clk high		P × 0.5-1 ^⁽¹⁾		ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI2 (vin2a_fld0 clock reference)	-2.5	2.5	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI2 (vin2a_fld0 clock reference)	-2.5	2.5	ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI3	-2.5	2.5	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI3	-2.5	2.5	ns

P = output vouti_clk period in ns.
All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx Processors for Use With Video Display SerDes for additional guidance.

Table 5-40 DPI Video Output i (i = 2, 3) Alternate Switching Characteristics^⁽²⁾

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
D1	t_c(clk)	Cycle time, output pixel clock vouti_clk	DPI2/3	6.06		ns
D2	t_w(clkL)	Pulse duration, output pixel clock vouti_clk low		P × 0.5-1 ^⁽¹⁾		ns
D3	t_w(clkH)	Pulse duration, output pixel clock vouti_clk high		P × 0.5-1 ^⁽¹⁾		ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI2 (vin2a_fld0 clock reference)	1.51	4.55	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI2 (vin2a_fld0 clock reference)	1.51	4.55	ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI3	1.51	4.55	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI3	1.51	4.55	ns

P = output vouti_clk period in ns.
All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx Processors for Use With Video Display SerDes for additional guidance.

Table 5-41 DPI Video Output i (i = 2, 3) MANUAL4 Switching Characteristics ^⁽²⁾

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
D1	t_c(clk)	Cycle time, output pixel clock vouti_clk	DPI2/3	6.06 ^⁽³⁾		ns
D2	t_w(clkL)	Pulse duration, output pixel clock vouti_clk low		P*0.5-1 ^⁽¹⁾		ns
D3	t_w(clkH)	Pulse duration, output pixel clock vouti_clk high		P*0.5-1 ^⁽¹⁾		ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI1	2.85	5.56	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI1	2.85	5.56	ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI2 (vin2a_fld0 clock reference)	2.85	5.56	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI2 (vin2a_fld0 clock reference)	2.85	5.56	ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI2 (xref_clk2 clock reference)	2.85	5.56	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI2 (xref_clk2 clock reference)	2.85	5.56	ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI3	2.85	5.56	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI3	2.85	5.56	ns

P = output vouti_clk period in ns.
All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx Processors for Use With Video Display SerDes for additional guidance.

Table 5-42 DPI Video Output i (i = 2, 3) MANUAL5 Switching Characteristics ^⁽²⁾

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
D1	t_c(clk)	Cycle time, output pixel clock vouti_clk	DPI2/3	6.06 ^⁽³⁾		ns
D2	t_w(clkL)	Pulse duration, output pixel clock vouti_clk low		P*0.5-1 ^⁽¹⁾		ns
D3	t_w(clkH)	Pulse duration, output pixel clock vouti_clk high		P*0.5-1 ^⁽¹⁾		ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI1	3.55	6.61	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI1	3.55	6.61	ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI2 (vin2a_fld0 clock reference)	3.55	6.61	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI2 (vin2a_fld0 clock reference)	3.55	6.61	ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI2 (xref_clk2 clock reference)	3.55	6.61	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI2 (xref_clk2 clock reference)	3.55	6.61	ns
D5	t_d(clk-ctlV)	Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid	DPI3	3.55	6.61	ns
D6	t_d(clk-dV)	Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid	DPI3	3.55	6.61	ns

P = output vouti_clk period in ns.
All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx Processors for Use With Video Display SerDes for additional guidance.

DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_DSS_01.gif

Figure 5-22 DPI Video Output^⁽¹⁾^⁽²⁾^⁽³⁾

The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.

In Table 5-43 are presented the specific groupings of signals (IOSET) for use with VOUT2.

Table 5-43 VOUT2 IOSETs

SIGNALS	IOSET1
SIGNALS	BALL	MUX
vout2_d23	C8	4
vout2_d22	B9	4
vout2_d21	A7	4
vout2_d20	A9	4
vout2_d19	A8	4
vout2_d18	A11	4
vout2_d17	F10	4
vout2_d16	A10	4
vout2_d15	B10	4
vout2_d14	E10	4
vout2_d13	D10	4
vout2_d12	C10	4
vout2_d11	B11	4
vout2_d10	D11	4
vout2_d9	C11	4
vout2_d8	B12	4
vout2_d7	A12	4
vout2_d6	A13	4
vout2_d5	E11	4
vout2_d4	F11	4
vout2_d3	B13	4
vout2_d2	E13	4
vout2_d1	C13	4
vout2_d0	D13	4
vout2_vsync	B8	4
vout2_hsync	E8	4
vout2_clk	C7	4
vout2_fld	D8	4
vout2_de	B7	4

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-32 and described in Device TRM, Control Module Chapter.

Virtual IO Timings Modes must be used to ensure some IO timings for VOUT3. See Table 5-29Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-44Virtual Functions Mapping for VOUT3 for a definition of the Virtual modes.

Table 5-44 presents the values for DELAYMODE bitfield.

Table 5-44 Virtual Functions Mapping for DSS VOUT3

BALL	BALL NAME	Delay Mode Value	MUXMODE
BALL	BALL NAME	DSS_VIRTUAL1	3
B4	gpmc_ad15	14	vout3_d15
K4	gpmc_a8	15	vout3_hsync
D1	gpmc_ad4	14	vout3_d4
F1	gpmc_ad0	14	vout3_d0
C4	gpmc_ad13	14	vout3_d13
L2	gpmc_a2	15	vout3_d18
E2	gpmc_ad1	14	vout3_d1
K3	gpmc_a4	15	vout3_d20
J1	gpmc_a6	15	vout3_d22
A3	gpmc_ad14	14	vout3_d14
M2	gpmc_a1	15	vout3_d17
G3	gpmc_cs3	15	vout3_clk
H1	gpmc_a9	15	vout3_vsync
B3	gpmc_ad11	14	vout3_d11
B1	gpmc_ad6	14	vout3_d6
E1	gpmc_ad2	14	vout3_d2
C1	gpmc_ad3	14	vout3_d3
K1	gpmc_a7	15	vout3_d23
L1	gpmc_a3	15	vout3_d19
A2	gpmc_ad10	14	vout3_d10
B2	gpmc_ad7	14	vout3_d7
J2	gpmc_a10	15	vout3_de
K2	gpmc_a5	15	vout3_d21
C2	gpmc_ad8	14	vout3_d8
D2	gpmc_ad5	14	vout3_d5
M1	gpmc_a0	15	vout3_d16
C3	gpmc_ad12	14	vout3_d12
L3	gpmc_a11	15	vout3_fld
D3	gpmc_ad9	14	vout3_d9

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to ensure some IO timings for VOUT2. See Table 5-29, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-45, Manual Functions Mapping for DSS VOUT2 IOSET1 for a definition of the Manual modes.

Table 5-45 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-45 Manual Functions Mapping for DSS VOUT2 IOSET1

BALL	BALL NAME	VOUT2_IOSET1 _MANUAL1		VOUT2_IOSET1 _MANUAL2		VOUT2_IOSET1 _MANUAL3		VOUT2_IOSET1 _MANUAL4		VOUT2_IOSET1 _MANUAL5		CFG REGISTER	MUXMODE
BALL	BALL NAME	A_DELAY (ps)	G_DELAY (ps)	A_DELAY (ps)	G_DELAY (ps)	A_DELAY (ps)	G_DELAY (ps)	A_DELAY (ps)	G_DELAY (ps)	A_DELAY (ps)	G_DELAY (ps)	CFG REGISTER	4
D8	vin2a_clk0	2571	0	1059	0	1025	0	4110	0	4980	0	CFG_VIN2A_CLK0_OUT	vout2_fld
C8	vin2a_d0	2124	0	589	0	577	0	3613	0	4483	0	CFG_VIN2A_D0_OUT	vout2_d23
B9	vin2a_d1	2103	0	568	0	557	0	3442	0	4312	0	CFG_VIN2A_D1_OUT	vout2_d22
D10	vin2a_d10	2091	0	557	0	545	0	3430	0	4200	0	CFG_VIN2A_D10_OUT	vout2_d13
C10	vin2a_d11	2142	0	608	0	596	0	3481	0	4251	0	CFG_VIN2A_D11_OUT	vout2_d12
B11	vin2a_d12	2920	385	1816	255	1783	276	3943	601	4713	601	CFG_VIN2A_D12_OUT	vout2_d11
D11	vin2a_d13	2776	322	1872	192	1838	213	3799	538	4669	538	CFG_VIN2A_D13_OUT	vout2_d10
C11	vin2a_d14	2904	0	1769	0	1757	0	3869	174	4739	174	CFG_VIN2A_D14_OUT	vout2_d9
B12	vin2a_d15	2670	257	1665	127	1632	148	3792	473	4662	473	CFG_VIN2A_D15_OUT	vout2_d8
A12	vin2a_d16	2814	155	1908	31	1878	43	3837	371	4707	371	CFG_VIN2A_D16_OUT	vout2_d7
A13	vin2a_d17	3002	199	1897	69	1865	89	4024	415	4894	415	CFG_VIN2A_D17_OUT	vout2_d6
E11	vin2a_d18	1893	0	358	0	347	0	3432	0	4302	0	CFG_VIN2A_D18_OUT	vout2_d5
F11	vin2a_d19	1698	0	163	0	151	0	3237	0	4007	0	CFG_VIN2A_D19_OUT	vout2_d4
A7	vin2a_d2	2193	0	658	0	646	0	3531	0	4401	0	CFG_VIN2A_D2_OUT	vout2_d21
B13	vin2a_d20	1736	0	202	0	190	0	3075	0	3945	0	CFG_VIN2A_D20_OUT	vout2_d3
E13	vin2a_d21	1636	0	101	0	89	0	3074	0	3944	0	CFG_VIN2A_D21_OUT	vout2_d2
C13	vin2a_d22	1628	0	93	0	81	0	3266	0	4036	0	CFG_VIN2A_D22_OUT	vout2_d1
D13	vin2a_d23	1538	0	0	0	0	0	2968	0	3838	0	CFG_VIN2A_D23_OUT	vout2_d0
A9	vin2a_d3	1997	0	462	0	450	0	3335	0	4205	0	CFG_VIN2A_D3_OUT	vout2_d20
A8	vin2a_d4	2528	0	993	0	982	0	3867	0	4537	0	CFG_VIN2A_D4_OUT	vout2_d19
A11	vin2a_d5	2038	0	503	0	492	0	3577	0	4347	0	CFG_VIN2A_D5_OUT	vout2_d18
F10	vin2a_d6	1746	0	211	0	200	0	3285	0	4055	0	CFG_VIN2A_D6_OUT	vout2_d17
A10	vin2a_d7	2213	0	678	0	666	0	3552	0	4272	0	CFG_VIN2A_D7_OUT	vout2_d16
B10	vin2a_d8	2268	0	733	0	721	0	3607	0	4277	0	CFG_VIN2A_D8_OUT	vout2_d15
E10	vin2a_d9	2170	0	635	0	623	0	3509	0	4379	0	CFG_VIN2A_D9_OUT	vout2_d14
B7	vin2a_de0	2102	0	568	0	556	0	3841	0	4611	0	CFG_VIN2A_DE0_OUT	vout2_de
C7	vin2a_fld0	0	983	1398	1185	1385	1202	0	994	0	994	CFG_VIN2A_FLD0_OUT	vout2_clk
E8	vin2a_hsync0	2482	0	974	0	936	0	4021	0	4891	0	CFG_VIN2A_HSYNC0_OUT	vout2_hsync
B8	vin2a_vsync0	2296	0	784	0	750	0	3935	0	4805	0	CFG_VIN2A_VSYNC0_OUT	vout2_vsync

Manual IO Timings Modes must be used to ensure some IO timings for VOUT3. See Table 5-29, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-46, Manual Functions Mapping for DSS VOUT3 for a definition of the Manual modes.

Table 5-46 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-46 Manual Functions Mapping for DSS VOUT3

BALL	BALL NAME	VOUT3_MANUAL1		VOUT3_MANUAL4		VOUT3_MANUAL5		CFG REGISTER	MUXMODE
BALL	BALL NAME	A_DELAY (ps)	G_DELAY (ps)	A_DELAY (ps)	G_DELAY (ps)	A_DELAY (ps)	G_DELAY (ps)	CFG REGISTER	3
M1	gpmc_a0	2395	0	3909	0	4779	0	CFG_GPMC_A0_OUT	vout3_d16
M2	gpmc_a1	2412	0	3957	0	4827	0	CFG_GPMC_A1_OUT	vout3_d17
J2	gpmc_a10	2473	0	3980	0	4850	0	CFG_GPMC_A10_OUT	vout3_de
L3	gpmc_a11	2906	0	4253	0	5123	0	CFG_GPMC_A11_OUT	vout3_fld
L2	gpmc_a2	2360	0	3873	0	4743	0	CFG_GPMC_A2_OUT	vout3_d18
L1	gpmc_a3	2391	0	4112	0	4982	0	CFG_GPMC_A3_OUT	vout3_d19
K3	gpmc_a4	2626	0	4336	0	5206	0	CFG_GPMC_A4_OUT	vout3_d20
K2	gpmc_a5	2338	0	3840	0	4710	0	CFG_GPMC_A5_OUT	vout3_d21
J1	gpmc_a6	2374	0	3913	0	4783	0	CFG_GPMC_A6_OUT	vout3_d22
K1	gpmc_a7	2432	0	3947	0	4817	0	CFG_GPMC_A7_OUT	vout3_d23
K4	gpmc_a8	3155	0	4309	105	5179	105	CFG_GPMC_A8_OUT	vout3_hsync
H1	gpmc_a9	2309	0	3842	0	4712	0	CFG_GPMC_A9_OUT	vout3_vsync
F1	gpmc_ad0	2360	0	3652	0	4522	0	CFG_GPMC_AD0_OUT	vout3_d0
E2	gpmc_ad1	2420	0	3762	0	4632	0	CFG_GPMC_AD1_OUT	vout3_d1
A2	gpmc_ad10	2235	0	3456	0	4326	0	CFG_GPMC_AD10_OUT	vout3_d10
B3	gpmc_ad11	2253	0	3584	0	4454	0	CFG_GPMC_AD11_OUT	vout3_d11
C3	gpmc_ad12	1949	427	3589	0	4459	0	CFG_GPMC_AD12_OUT	vout3_d12
C4	gpmc_ad13	2318	0	3547	0	4417	0	CFG_GPMC_AD13_OUT	vout3_d13
A3	gpmc_ad14	2123	0	3302	0	4172	0	CFG_GPMC_AD14_OUT	vout3_d14
B4	gpmc_ad15	2195	29	3532	0	4402	0	CFG_GPMC_AD15_OUT	vout3_d15
E1	gpmc_ad2	2617	0	3859	0	4729	0	CFG_GPMC_AD2_OUT	vout3_d2
C1	gpmc_ad3	2350	0	3590	0	4460	0	CFG_GPMC_AD3_OUT	vout3_d3
D1	gpmc_ad4	2324	0	3534	0	4404	0	CFG_GPMC_AD4_OUT	vout3_d4
D2	gpmc_ad5	2371	0	3609	0	4479	0	CFG_GPMC_AD5_OUT	vout3_d5
B1	gpmc_ad6	2231	0	3416	0	4286	0	CFG_GPMC_AD6_OUT	vout3_d6
B2	gpmc_ad7	2440	0	3661	0	4531	0	CFG_GPMC_AD7_OUT	vout3_d7
C2	gpmc_ad8	2479	0	3714	0	4584	0	CFG_GPMC_AD8_OUT	vout3_d8
D3	gpmc_ad9	2355	0	3593	0	4463	0	CFG_GPMC_AD9_OUT	vout3_d9
G3	gpmc_cs3	0	641	0	905	0	905	CFG_GPMC_CS3_OUT	vout3_clk

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5.10.6.4 DSS

Table 5-39 DPI Video Output i (i = 2, 3) Default Switching Characteristics(1)(2)

Table 5-40 DPI Video Output i (i = 2, 3) Alternate Switching Characteristics(2)

Table 5-41 DPI Video Output i (i = 2, 3) MANUAL4 Switching Characteristics (2)

Table 5-42 DPI Video Output i (i = 2, 3) MANUAL5 Switching Characteristics (2)

Table 5-43 VOUT2 IOSETs

Table 5-44 Virtual Functions Mapping for DSS VOUT3

Table 5-45 Manual Functions Mapping for DSS VOUT2 IOSET1

Table 5-46 Manual Functions Mapping for DSS VOUT3

Table 5-39 DPI Video Output i (i = 2, 3) Default Switching Characteristics^{⁽¹⁾⁽²⁾}

Table 5-40 DPI Video Output i (i = 2, 3) Alternate Switching Characteristics^⁽²⁾

Table 5-41 DPI Video Output i (i = 2, 3) MANUAL4 Switching Characteristics ^⁽²⁾

Table 5-42 DPI Video Output i (i = 2, 3) MANUAL5 Switching Characteristics ^⁽²⁾