Refer to the PDF data sheet for device specific package drawings
Processor cores:
Memory subsystem:
Virtualization:
Device security (on select part numbers):
Functional Safety:
High-speed interfaces:
Automotive interfaces:
Audio interfaces:
Flash memory interfaces:
Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.
Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.
Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).
PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) |
---|---|---|
DRA821U4-Q1 DRA821U4 |
ALM (FCBGA, 433) | 17.2 mm × 17.2 mm |
DRA821U2-Q1 DRA821U2 |
ALM (FCBGA, 433) | 17.2 mm × 17.2 mm |
XJ7200GB | ALM (FCBGA, 433) | 17.2 mm × 17.2 mm |
Figure 3-1 is functional block diagram for the device.
Changes from December 17, 2022 to June 30, 2023 (from Revision D (December 2022) to Revision E (June 2023))
Table 5-1 shows the features of the SoC, highlighting the differences.
FEATURES | REFERENCE NAME | DRA821U4 | DRA821U2 |
---|---|---|---|
Features | |||
PROCESSORS AND ACCELERATORS | |||
Speed Grades (see Table 7-1) | T, L, E | E, C | |
Arm Cortex-A72 Microprocessor Subsystem | Arm A72 | Dual Core | Dual Core |
Arm Cortex-R5F | Arm R5F | Quad Core | Quad Core |
Lockstep | Optional(5) | Optional(5) | |
Device Management Security Controller | DMSC | Yes | Yes |
Security Accelerators | SA | Yes | Yes |
SAFETY AND SECURITY | |||
Safety Targeted | Safety | Optional(5) | Optional(5) |
Device Security | Security | Optional(6) | Optional(6) |
AEC-Q100 Qualified | Q1 | Optional(7) | Optional(7) |
PROGRAM AND DATA STORAGE | |||
On-Chip Shared Memory (RAM) in MAIN Domain | OCSRAM | 512KB SRAM | 512KB SRAM |
On-Chip Shared Memory (RAM) in MCU Domain | MCU_MSRAM | 1MB SRAM | 1MB SRAM |
Multicore Shared Memory Controller | MSMC | 1MB (On-Chip SRAM with ECC) | 1MB (On-Chip SRAM with ECC) |
LPDDR4 DDR Subsystem | DDRSS | Up to 8GB (16/32-bit data) with inline ECC | Up to 8GB (16/32-bit data) with inline ECC |
SECDED | 7-bit | 7-bit | |
General-Purpose Memory Controller | GPMC | Up to 1GB with ECC | Up to 1GB with ECC |
PERIPHERALS | |||
Modular Controller Area Network Interface with Full CAN-FD Support | MCAN | 20 | 20 |
Navigator Subsystem | NAVSS | 2 | 2 |
General-Purpose I/O | GPIO | Up to 141 | Up to 141 |
Inter-Integrated Circuit Interface | I2C | 10 | 10 |
Improved Inter-Integrated Circuit Interface | I3C | 2 | 2 |
Analog-to-Digital Converter | ADC | 1 | 1 |
Multichannel Serial Peripheral Interface | MCSPI | 11 (8) | 11 (8) |
Multichannel Audio Serial Port | MCASP0 | 16 Serializers | 16 Serializers |
MCASP1 | 12 Serializers | 12 Serializers | |
MCASP2 | 6 Serializers | 6 Serializers | |
MultiMedia Card/ Secure Digital Interface | MMCSD0 | eMMC (8-bits) | eMMC (8-bits) |
MMCSD1 | SD/SDIO (4-bits) |
SD/SDIO (4-bits) |
|
Flash Subsystem (FSS) | OSPI | 8-bits(4) | 8-bits(4) |
HyperBus | Yes(4) | Yes(4) | |
PCI Express Port with Integrated PHY | PCIE | Up to Four Lanes(1) | Up to Four Lanes(1) |
Ethernet Interface | CPSW2G | 1 Port(3) | 1 Port(3) |
CPSW5G | 4 Ports (1)(2) | 2 Ports(1)(2) | |
General-Purpose Timers | TIMER | 30 | 30 |
Enhanced Pulse-Width Modulator Module | EPWM | 6 | 6 |
Enhanced Capture Module | ECAP | 3 | 3 |
Enhanced Quadrature Encoder Pulse Module | EQEP | 3 | 3 |
Universal Asynchronous Receiver and Transmitter | UART | 12 | 12 |
Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD) Ports with SS PHY | USB | Yes(1) | Yes(1) |
Companion Products for DRA821U Review products that are frequently purchased or used in conjunction with this product.
Software Development Kit for DRA821 Jacinto™ Processors Processor SDK RTOS (PSDK RTOS) can be used together with Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX), to form a multi-processor software development platform for DRA821 SoCs within the TI’s Jacinto™ Processors platform. The SDK provides a comprehensive set of software tools and components to help users develop and deploy their applications on supported J7 SoCs. PSDK RTOS and either PSDK Linux or PSDK QNX can be used together to implement various use-cases in factory and building automation, and gateway systems.
DRA821 Evaluation Module The J700XSOMXEVM paired with the J721EXCP01EVM Common Processor Board is an evaluation platform designed to speed up development efforts and reduce time to market for networking applications throughout automotive and industrial markets.
The EVM is supported by Processor SDK, which includes foundational drivers, compute and vision kernels, and example application frameworks and demonstrations that show you how to take advantage of the powerful, heterogeneous architecture of Jacinto 7 processors.
Application Notes and White Paper Gateway application processor with integrated system MCU.
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package.
Figure 6-1 shows the ball locations for the 433-ball flip chip ball grid array (FCBGA) package that are used in conjunction with Table 6-1 through Table 6-107 to locate signal names and ball grid numbers.