SPRSP57E april 2020 – june 2023 DRA821U , DRA821U-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Independent MCU and Main voltage domains enable an SoC’s MCU and Main processor sub-systems to operate independently. There are 2 reasons an SoC’s PDN design may need to support independent MCU and Main processor functionality. First is to provide flexibility to enable SoC low power modes that can significant reduce SoC power dissipation when processor operations are not needed. Second is to enable robustness to gain freedom from interference (FFI) of a single fault impacting both MCU and Main processor sub-systems which is especially beneficial if using the SoC’s MCU as the system safety monitoring processor. The number of additional PDN power rails needed is dependent upon number of different MCU IO signaling voltage levels. If only 1.8V IO signaling is used, the only 2 additional power rails could be required. If both 1.8 and 3.3V IO signaling is desired, then 4 additional power rails could be needed.
Time stamp markers show approximate elapsed times that are dependent upon PDN feature set, component selection and power mapping. Values shown are typical for PDNs supporting independent MCU and Main voltage domains but could vary based upon PDN design.
Time Stamp definitions and (typical values for reference only):