SPRSP57E april   2020  – june 2023 DRA821U , DRA821U-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
        2. 6.3.2.2 DDRSS Mapping
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 WKUP Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
        3. 6.3.4.3 WKUP Domain
      5. 6.3.5  I3C
        1. 6.3.5.1 MAIN Domain
        2. 6.3.5.2 MCU Domain
      6. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
        2. 6.3.8.2 MCU Domain
        3. 6.3.8.3 WKUP Domain
      9. 6.3.9  MDIO
        1. 6.3.9.1 MCU Domain
        2. 6.3.9.2 MAIN Domain
      10. 6.3.10 CPSW2G
        1. 6.3.10.1 MCU Domain
      11. 6.3.11 CPSW5G
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 ECAP
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 EQEP
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 EPWM
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 USB
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 SERDES
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 OSPI
        1. 6.3.17.1 MCU Domain
      18. 6.3.18 Hyperbus
        1. 6.3.18.1 MCU Domain
      19. 6.3.19 GPMC
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 MMC
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 CPTS
        1. 6.3.21.1 MAIN Domain
        2. 6.3.21.2 MCU Domain
      22. 6.3.22 MCASP
        1. 6.3.22.1 MAIN Domain
      23. 6.3.23 DMTIMER
        1. 6.3.23.1 MAIN Domain
        2. 6.3.23.2 MCU Domain
      24. 6.3.24 Emulation and Debug
        1. 6.3.24.1 MAIN Domain
      25. 6.3.25 System and Miscellaneous
        1. 6.3.25.1 Boot Mode Configuration
          1. 6.3.25.1.1 MAIN Domain
          2. 6.3.25.1.2 MCU Domain
        2. 6.3.25.2 Clock
          1. 6.3.25.2.1 MAIN Domain
          2. 6.3.25.2.2 WKUP Domain
        3. 6.3.25.3 System
          1. 6.3.25.3.1 MAIN Domain
          2. 6.3.25.3.2 WKUP Domain
          3. 6.3.25.3.3 VMON
        4. 6.3.25.4 EFUSE
      26. 6.3.26 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Power-On-Hours (POH)
    5. 7.5 Operating Performance Points
    6. 7.6 Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  ADC12BT Electrical Characteristics
      7. 7.6.7  LVCMOS Electrical Characteristics
      8. 7.6.8  USB2PHY Electrical Characteristics
      9. 7.6.9  SERDES Electrical Characteristics
      10. 7.6.10 DDR Electrical Characteristics
    7. 7.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8 Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Timing Parameters and Information
      2. 7.9.2 Power Supply Sequencing
        1. 7.9.2.1 Power Supply Slew Rate Requirement
        2. 7.9.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.9.2.4 Independent MCU and Main Domains Power- Up Sequencing
        5. 7.9.2.5 Independent MCU and Main Domains Power- Down Sequencing
        6. 7.9.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.9.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.9.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.9.3 System Timing
        1. 7.9.3.1 Reset Timing
        2. 7.9.3.2 Safety Signal Timing
        3. 7.9.3.3 Clock Timing
      4. 7.9.4 Clock Specifications
        1. 7.9.4.1 Input Clocks / Oscillators
          1. 7.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.9.4.1.1.1 Load Capacitance
            2. 7.9.4.1.1.2 Shunt Capacitance
          2. 7.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.9.4.1.3.1 Load Capacitance
            2. 7.9.4.1.3.2 Shunt Capacitance
          4. 7.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.9.4.1.5 Auxiliary OSC1 Not Used
          6. 7.9.4.1.6 WKUP_LF_CLKIN Internal Oscillator Clock Source
          7. 7.9.4.1.7 WKUP_LF_CLKIN Not Used
        2. 7.9.4.2 Output Clocks
        3. 7.9.4.3 PLLs
        4. 7.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 7.9.4.5 Interface Clock Specifications
          1. 7.9.4.5.1 Interface Clock Terminology
          2. 7.9.4.5.2 Interface Clock Frequency
      5. 7.9.5 Peripherals
        1. 7.9.5.1  ATL
          1. 7.9.5.1.1 ATL_PCLK Timing Requirements
          2. 7.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.9.5.2  CPSW2G
          1. 7.9.5.2.1 CPSW2G RMII Timings
            1. 7.9.5.2.1.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.9.5.2.1.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.9.5.2.1.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          2. 7.9.5.2.2 CPSW2G RGMII Timings
            1. 7.9.5.2.2.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.9.5.2.2.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.9.5.2.2.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.9.5.2.2.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        3. 7.9.5.3  CPSW5G
          1. 7.9.5.3.1 CPSW5G MDIO Interface Timings
          2. 7.9.5.3.2 CPSW5G RMII Timings
            1. 7.9.5.3.2.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.9.5.3.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.9.5.3.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 7.9.5.3.3 CPSW5G RGMII Timings
            1. 7.9.5.3.3.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.9.5.3.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.9.5.3.3.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.9.5.3.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        4. 7.9.5.4  DDRSS
        5. 7.9.5.5  ECAP
          1. 7.9.5.5.1 Timing Requirements for ECAP
          2. 7.9.5.5.2 Switching Characteristics for ECAP
        6. 7.9.5.6  EPWM
          1. 7.9.5.6.1 Timing Requirements for EPWM
          2. 7.9.5.6.2 Switching Characteristics for EPWM
        7. 7.9.5.7  EQEP
          1. 7.9.5.7.1 Timing Requirements for EQEP
          2. 7.9.5.7.2 Switching Characteristics for EQEP
        8. 7.9.5.8  GPIO
        9. 7.9.5.9  GPMC
          1. 7.9.5.9.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.9.5.9.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.9.5.9.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.9.5.9.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.9.5.9.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.9.5.9.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.9.5.9.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.9.5.9.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.9.5.9.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        10. 7.9.5.10 HyperBus
          1. 7.9.5.10.1 Timing Requirements for HyperBus Initialization
          2. 7.9.5.10.2 HyperBus 166 MHz Switching Characteristics
          3. 7.9.5.10.3 HyperBus 100 MHz Switching Characteristics
        11. 7.9.5.11 I2C
        12. 7.9.5.12 I3C
        13. 7.9.5.13 MCAN
        14. 7.9.5.14 MCASP
          1. 7.9.5.14.1 Timing Requirements for MCASP
        15. 7.9.5.15 MCSPI
          1. 7.9.5.15.1 MCSPI — Controller Mode
          2. 7.9.5.15.2 MCSPI — Peripheral Mode
        16. 7.9.5.16 eMMC/SD/SDIO
          1. 7.9.5.16.1 MMCSD0 - eMMC Interface
            1. 7.9.5.16.1.1 Legacy SDR Mode
            2. 7.9.5.16.1.2 High Speed SDR Mode
            3. 7.9.5.16.1.3 High Speed DDR Mode
            4. 7.9.5.16.1.4 HS200 Mode
            5. 7.9.5.16.1.5 HS400 Mode
          2. 7.9.5.16.2 MMCSDi — MMCSD1 — SD/SDIO Interface
            1. 7.9.5.16.2.1 Default speed Mode
            2. 7.9.5.16.2.2 High Speed Mode
            3. 7.9.5.16.2.3 UHS–I SDR12 Mode
            4. 7.9.5.16.2.4 UHS–I SDR25 Mode
            5. 7.9.5.16.2.5 UHS–I SDR50 Mode
            6. 7.9.5.16.2.6 UHS–I DDR50 Mode
            7. 7.9.5.16.2.7 UHS–I SDR104 Mode
        17. 7.9.5.17 NAVSS
          1. 7.9.5.17.1 Timing Requirements for CPTS Input
          2. 7.9.5.17.2 Switching Characteristics for CPTS Output
        18. 7.9.5.18 OSPI
          1. 7.9.5.18.1 OSPI With Data Training
            1. 7.9.5.18.1.1 OSPI Switching Characteristics – Data Training
          2. 7.9.5.18.2 OSPI Without Data Training
            1. 7.9.5.18.2.1 OSPI Switching Characteristics – DDR Mode
            2. 7.9.5.18.2.2 OSPI Switching Characteristics – SDR Mode
            3. 7.9.5.18.2.3 OSPI Timing Requirements – DDR Mode
            4. 7.9.5.18.2.4 OSPI Timing Requirements – SDR Mode
        19. 7.9.5.19 PCIE
        20. 7.9.5.20 Timers
          1. 7.9.5.20.1 Timing Requirements for Timers
          2. 7.9.5.20.2 Switching Characteristics for Timers
        21. 7.9.5.21 UART
          1. 7.9.5.21.1 UART Timing Requirements
          2. 7.9.5.21.2 UART Switching Characteristics
        22. 7.9.5.22 USB
      6. 7.9.6 Emulation and Debug
        1. 7.9.6.1 Debug Trace
        2. 7.9.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)
          1. 7.9.6.2.1 JTAG Electrical Data and Timing
            1. 7.9.6.2.1.1 Timing Requirements for IEEE 1149.1 JTAG
            2. 7.9.6.2.1.2 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
    3. 8.3 Other Subsystems
      1. 8.3.1 MSMC
      2. 8.3.2 NAVSS
        1. 8.3.2.1 NAVSS0
        2. 8.3.2.2 MCU_NAVSS
      3. 8.3.3 PDMA Controller
      4. 8.3.4 Peripherals
        1. 8.3.4.1  ADC
        2. 8.3.4.2  ATL
        3. 8.3.4.3  CPSW2G
        4. 8.3.4.4  CPSW5G
        5. 8.3.4.5  DCC
        6. 8.3.4.6  DDRSS
        7. 8.3.4.7  ECAP
        8. 8.3.4.8  EPWM
        9. 8.3.4.9  ELM
        10. 8.3.4.10 ESM
        11. 8.3.4.11 EQEP
        12. 8.3.4.12 GPIO
        13. 8.3.4.13 GPMC
        14. 8.3.4.14 Hyperbus
        15. 8.3.4.15 I2C
        16. 8.3.4.16 I3C
        17. 8.3.4.17 MCAN
        18. 8.3.4.18 MCASP
        19. 8.3.4.19 MCRC Controller
        20. 8.3.4.20 MCSPI
        21. 8.3.4.21 MMC/SD
        22. 8.3.4.22 OSPI
        23. 8.3.4.23 PCIE
        24. 8.3.4.24 SerDes
        25. 8.3.4.25 WWDT
        26. 8.3.4.26 Timers
        27. 8.3.4.27 UART
        28. 8.3.4.28 USB
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 USB VBUS Design Guidelines
      4. 9.3.4 System Power Supply Monitor Design Guidelines
      5. 9.3.5 High Speed Differential Signal Routing Guidance
      6. 9.3.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALM|433
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.3.1 MAIN Domain

Table 6-5 GPIO0 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
GPIO0_0General Purpose Input/OutputIOU6
GPIO0_1General Purpose Input/OutputIOT19
GPIO0_2General Purpose Input/OutputIOAA17
GPIO0_3General Purpose Input/OutputIOY15
GPIO0_4General Purpose Input/OutputIOAA20
GPIO0_5General Purpose Input/OutputIOY17
GPIO0_6General Purpose Input/OutputIOY16
GPIO0_7General Purpose Input/OutputIOV17
GPIO0_8General Purpose Input/OutputIOAA19
GPIO0_9General Purpose Input/OutputIOV18
GPIO0_10General Purpose Input/OutputIOV20
GPIO0_11General Purpose Input/OutputIOW21
GPIO0_12General Purpose Input/OutputIOV16
GPIO0_13General Purpose Input/OutputIOY18
GPIO0_14General Purpose Input/OutputIOY19
GPIO0_15General Purpose Input/OutputIOY21
GPIO0_16General Purpose Input/OutputIOW16
GPIO0_17General Purpose Input/OutputIOW15
GPIO0_18General Purpose Input/OutputIOY20
GPIO0_19General Purpose Input/OutputIOV21
GPIO0_20General Purpose Input/OutputIOV19
GPIO0_21General Purpose Input/OutputIOT13
GPIO0_22General Purpose Input/OutputIOU14
GPIO0_23General Purpose Input/OutputIOU16
GPIO0_24General Purpose Input/OutputIOU15
GPIO0_25General Purpose Input/OutputIOT15
GPIO0_26General Purpose Input/OutputIOU19
GPIO0_27General Purpose Input/OutputIOT14
GPIO0_28General Purpose Input/OutputIOU18
GPIO0_29General Purpose Input/OutputIOU17
GPIO0_30General Purpose Input/OutputIOU20
GPIO0_31General Purpose Input/OutputIOY14
GPIO0_32General Purpose Input/OutputIOY13
GPIO0_33General Purpose Input/OutputIOAA15
GPIO0_34General Purpose Input/OutputIOAA14
GPIO0_35General Purpose Input/OutputIOAA18
GPIO0_36General Purpose Input/OutputIOAA16
GPIO0_37General Purpose Input/OutputIOW17
GPIO0_38General Purpose Input/OutputIOW20
GPIO0_39General Purpose Input/OutputIOV14
GPIO0_40General Purpose Input/OutputIOV13
GPIO0_41General Purpose Input/OutputIOU12
GPIO0_42General Purpose Input/OutputIOW14
GPIO0_43General Purpose Input/OutputIOW19
GPIO0_44General Purpose Input/OutputIOU13
GPIO0_45General Purpose Input/OutputIOV15
GPIO0_46General Purpose Input/OutputIOU21
GPIO0_47General Purpose Input/OutputIOT16
GPIO0_48General Purpose Input/OutputIOT17
GPIO0_49General Purpose Input/OutputIOT18
GPIO0_50General Purpose Input/OutputIOT20
GPIO0_51General Purpose Input/OutputIOW3
GPIO0_52General Purpose Input/OutputIOU5
GPIO0_53General Purpose Input/OutputIOY1
GPIO0_54General Purpose Input/OutputIOV4
GPIO0_55General Purpose Input/OutputIOT5
GPIO0_56General Purpose Input/OutputIOV3
GPIO0_57General Purpose Input/OutputIOW2
GPIO0_58General Purpose Input/OutputIOU3
GPIO0_59General Purpose Input/OutputIOT3
GPIO0_60General Purpose Input/OutputIOV1
GPIO0_61General Purpose Input/OutputIOW1
GPIO0_62General Purpose Input/OutputION19
GPIO0_63General Purpose Input/OutputION20
GPIO0_64General Purpose Input/OutputION21
GPIO0_65General Purpose Input/OutputIOM19
GPIO0_66General Purpose Input/OutputIOP21
GPIO0_67General Purpose Input/OutputIOM20
GPIO0_68General Purpose Input/OutputIOT4