SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
VDD_CORE | MAIN domain core supply | –0.3 | 1.05 | V | |
VDD_MCU | MCUSS core supply | –0.3 | 1.05 | V | |
VDD_CPU | CPU core supply | –0.3 | 1.05 | V | |
VDDA_0P8_DLL_MMC0 | MMC0 DLL analog supply | –0.3 | 1.05 | V | |
VDDAR_CORE | MAIN domain RAM supply | –0.3 | 1.05 | V | |
VDDAR_MCU | MCUSS RAM supply | –0.3 | 1.05 | V | |
VDDAR_CPU | CPU RAM supply | –0.3 | 1.05 | V | |
VDDA_0P8_DP | Displayport SERDES analog supply low | –0.3 | 1.05 | V | |
VDDA_0P8_DP_C | Displayport SERDES clock supply | –0.3 | 1.05 | V | |
VDDA_0P8_DSITX | DSITX clock supply | –0.3 | 1.05 | V | |
VDDA_0P8_DSITX_C | DSITX clock supply | –0.3 | 1.05 | V | |
VDDA_0P8_CSIRX | CSIRX analog supply low | –0.3 | 1.05 | V | |
VDDA_0P8_SERDES0_1 | SERDES0-1 analog supply low | –0.3 | 1.05 | V | |
VDDA_0P8_SERDES2_3 | SERDES2-3 analog supply low | –0.3 | 1.05 | V | |
VDDA_0P8_SERDES_C0_1 | SERDES0-1 clock supply | –0.3 | 1.05 | V | |
VDDA_0P8_SERDES_C2_3 | SERDES2-3 clock supply | –0.3 | 1.05 | V | |
VDDA_0P8_USB | USB0-1 0.8 V analog supply | –0.3 | 1.05 | V | |
VDDA_0P8_UFS | UFS analog supply low | –0.3 | 1.05 | V | |
VDDA_0P8_PLL_MLB | MLB PLL analog supply | –0.3 | 1.05 | V | |
VDDA_0P8_PLL_DDR | DDR PLL analog supply | –0.3 | 1.05 | V | |
VDDA_1P8_USB | USB0-1 1.8 V analog supply | –0.3 | 2.2 | V | |
VDDA_1P8_UFS | UFS analog supply high | –0.3 | 2.2 | V | |
VDDA_1P8_DP | Displayport SERDES analog supply high | –0.3 | 2.2 | V | |
VDDA_1P8_DSITX | DSITX analog supply high | –0.3 | 2.2 | V | |
VDDA_1P8_CSIRX | CSIRX analog supply high | –0.3 | 2.2 | V | |
VDDA_1P8_SERDES0_1 | SERDES0-1 analog supply high | –0.3 | 2.2 | V | |
VDDA_1P8_SERDES2_3 | SERDES2-3 analog supply high | –0.3 | 2.2 | V | |
VDDA_3P3_USB | USB0-1 3.3 V analog supply | –0.3 | 3.8 | V | |
VDDA_MCU_PLLGRP0 | Analog supply for MCU PLL Group 0 | –0.3 | 2.2 | V | |
VDDA_PLLGRP0 | Analog supply for Main PLL Group 0 | –0.3 | 2.2 | V | |
VDDA_PLLGRP1 | Analog supply for Main PLL Group 1 | –0.3 | 2.2 | V | |
VDDA_PLLGRP2 | Analog supply for Main PLL Group 2 | –0.3 | 2.2 | V | |
VDDA_PLLGRP3 | Analog supply for Main PLL Group 3 | –0.3 | 2.2 | V | |
VDDA_PLLGRP4 | Analog supply for Main PLL Group 4 | –0.3 | 2.2 | V | |
VDDA_PLLGRP5 | Analog supply for MAIN PLL Group 5 (DDR) | –0.3 | 2.2 | V | |
VDDA_PLLGRP6 | Analog supply for MAIN PLL Group 6 | –0.3 | 2.2 | V | |
VDDA_WKUP | Oscillator supply for WKUP domain | –0.3 | 2.2 | V | |
VDDA_ADC0 | ADC analog supply | –0.3 | 2.2 | V | |
VDDA_ADC1 | ADC analog supply | –0.3 | 2.2 | V | |
VDDA_MCU_TEMP | Analog supply for temperature sensor 0 in MCU domain | –0.3 | 2.2 | V | |
VDDA_POR_WKUP | WKUP domain analog supply | –0.3 | 2.2 | V | |
VDDA_1P8_MLB | MLB IO supply (6-pin interface) | –0.3 | 2.2 | V | |
VDDA_TEMP_0_1 | Analog supply for temperature sensor 0 | –0.3 | 2.2 | V | |
VDDA_TEMP_2_3 | Analog supply for temperature sensor 2 | –0.3 | 2.2 | V | |
VDDS_DDR | DDR inteface power supply | –0.3 | 1.2 | V | |
VDDS_DDR_BIAS | Bias supply for LPDDR4 | –0.3 | 1.2 | V | |
VDDS_DDR_C | IO power for DDR Memory Clock Bit (MCB) macro | –0.3 | 1.2 | V | |
VDDS_MMC0 | MMC0 IO supply | –0.3 | 2.2 | V | |
VDDS_OSC1 | HFOSC1 supply | –0.3 | 2.2 | V | |
VDDSHV0_MCU | IO supply MCUSS general IO group, and MCU and MAIN domain warm reset pins | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VDDSHV0 | IO supply for MAIN domain general | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VDDSHV1_MCU | IO supply for MCUSS IO group 1 | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VDDSHV1 | IO supply for MAIN domain IO group 1 | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VDDSHV2_MCU | IO supply for MCUSS IO group 2 | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VDDSHV2 | IO supply for MAIN domain IO group 2 | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VDDSHV3 | IO supply for MAIN domain IO group 3 | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VDDSHV4 | IO supply for MAIN domain IO group 4 | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VDDSHV5 | IO supply for MAIN domain IO group 5 | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VDDSHV6 | IO supply for MAIN domain IO group 6 | 1.8 V | –0.3 | 2.2 | V |
3.3 V | –0.3 | 3.8 | |||
VPP_CORE | Supply voltage range for CORE EFUSE domain | –0.3 | 1.89 | V | |
VPP_MCU | Supply voltage range for MCU EFUSE domain | –0.3 | 1.89 | V | |
USB0_VBUS(9) | Voltage range for USB VBUS comparator input | –0.3 | 3.6 | V | |
USB1_VBUS(9) | Voltage range for USB VBUS comparator input | –0.3 | 3.6 | V | |
Steady State Max. Voltage at all fail-safe IO pins | I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA, MCU_I2C0_SCL, MCU_I2C0_SDA, EXTINTn | –0.3 | 3.8 | V | |
MCU_PORz, PORz | –0.3 | 3.8 | V | ||
VMON_IR_VEXT | –0.3 | 2.2 | V | ||
VMON_ER_VSYS(7)(8) | –0.3 | 1.05 | V | ||
Steady State Max. Voltage at all other IO pins(3) | All other IO pins | –0.3 | IO supply voltage + 0.3 | V | |
Transient Overshoot and Undershoot specification at IO pin | 20% of IO supply voltage for up to 20% of signal
period (see Figure 6-1, IO Transient Voltage Ranges) |
0.2 × VDD(6) | V | ||
Latch-up Performance, Class II (125°C)(4) | I-Test | –100 | 100 | mA | |
Over-Voltage (OV) Test | NA | 1.5 × VDD(6) | V | ||
TSTG(5) | Storage temperature | –55 | +150 | °C |
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, NMIn, VMON_ER_VSYS, and VMON_IR_VEXT are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 6.1.