SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The device contains ATL module that can be used for asynchronous sample rate conversion of audio. The ATL calculates the error between two time bases, such as audio syncs, and optionally generates an averaged clock using cycle stealing via software.
For more information about ATL, see Audio Tracking Logic (ATL) section in Peripherals chapter in the device TRM.
Table 6-28 represents ATL timing conditions.
PARAMETER | MODE | MIN | MAX | UNIT | |
---|---|---|---|---|---|
INPUT CONDITIONS | |||||
SRI | Input slew rate | External reference CLK | 0.5 | 5 | V/ns |
OUTPUT CONDITIONS | |||||
CL | Output load capacitance | Internal reference CLK | 1 | 10 | pF |
Section 6.9.5.1.1, Section 6.9.5.1.2, Section 6.9.5.1.3, and Section 6.9.5.1.4 present timing requirements and switching characteristics for ATL.