SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description.
Table 6-100 represents UART timing conditions.
PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|
INPUT CONDITIONS | ||||
SRI | Input slew rate | 0.5 | 5 | V/ns |
OUTPUT CONDITIONS | ||||
CL | Output load capacitance | 1 | 30 | pF |
PCB CONNECTIVITY REQUIREMENTS | ||||
td(Trace Mismatch Delay) | Propagation delay mismatch across all traces | 100 | ps |
Section 6.9.5.24.1, Section 6.9.5.24.2, and Figure 6-120 present timing requirements and switching characteristics for UART interface.