SPRSP35K February   2019  – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
        2. 5.3.3.2 WKUP Domain
      4. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 MCU Domain
        3. 5.3.4.3 WKUP Domain
      5. 5.3.5  I3C
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
        2. 5.3.6.2 MCU Domain
      7. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
        2. 5.3.7.2 MCU Domain
      8. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
        2. 5.3.8.2 MCU Domain
        3. 5.3.8.3 WKUP Domain
      9. 5.3.9  MDIO
        1. 5.3.9.1 MCU Domain
      10. 5.3.10 CPSW2G
        1. 5.3.10.1 MCU Domain
      11. 5.3.11 CPSW9G
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 ECAP
        1. 5.3.12.1 MAIN Domain
      13. 5.3.13 EQEP
        1. 5.3.13.1 MAIN Domain
      14. 5.3.14 EHRPWM
        1. 5.3.14.1 MAIN Domain
      15. 5.3.15 USB
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 SERDES
        1. 5.3.16.1 MAIN Domain
      17. 5.3.17 OSPI
        1. 5.3.17.1 MCU Domain
      18. 5.3.18 Hyperbus
        1. 5.3.18.1 MCU Domain
      19. 5.3.19 GPMC
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 MMC
        1. 5.3.20.1 MAIN Domain
      21. 5.3.21 CPTS
        1. 5.3.21.1 MCU Domain
        2. 5.3.21.2 MAIN Domain
      22. 5.3.22 UFS
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 PRU_ICSSG [Currently Not Supported]
        1. 5.3.23.1 MAIN Domain
      24. 5.3.24 MCASP
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 DSS
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 DP
        1. 5.3.26.1 MAIN Domain
      27. 5.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 5.3.27.1 MAIN Domain
      28. 5.3.28 DSI_TX
        1. 5.3.28.1 MAIN Domain
      29. 5.3.29 VPFE
        1. 5.3.29.1 MAIN Domain
      30. 5.3.30 DMTIMER
        1. 5.3.30.1 MAIN Domain
        2. 5.3.30.2 MCU Domain
      31. 5.3.31 Emulation and Debug
        1. 5.3.31.1 MAIN Domain
      32. 5.3.32 System and Miscellaneous
        1. 5.3.32.1 Boot Mode Configuration
          1. 5.3.32.1.1 MAIN Domain
          2. 5.3.32.1.2 MCU Domain
        2. 5.3.32.2 Clock
          1. 5.3.32.2.1 MAIN Domain
          2. 5.3.32.2.2 WKUP Domain
        3. 5.3.32.3 System
          1. 5.3.32.3.1 MAIN Domain
          2. 5.3.32.3.2 WKUP Domain
        4. 5.3.32.4 EFUSE
      33. 5.3.33 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On-Hour (POH) Limits
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
    6. 6.6 Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  CSI-2/DSI D-PHY Electrical Characteristics
      7. 6.6.7  ADC12B Electrical Characteristics
      8. 6.6.8  MLB LVCMOS Electrical Characteristics
      9. 6.6.9  LVCMOS Electrical Characteristics
      10. 6.6.10 USB2PHY Electrical Characteristics
      11. 6.6.11 SerDes 4-L-PHY/2-L-PHY Electrical Characteristics
      12. 6.6.12 UFS M-PHY Electrical Characteristics
      13. 6.6.13 eDP/DP AUX-PHY Electrical Characteristics
      14. 6.6.14 DDR0 Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for ALF Package
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 6.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.9.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.9.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing
        6. 6.9.2.6 Entry and Exit of MCU Only State
        7. 6.9.2.7 Entry and Exit of DDR Retention State
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input and Output Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.9.4.1.1.1 Load Capacitance
            2. 6.9.4.1.1.2 Shunt Capacitance
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.9.4.1.3.1 Load Capacitance
            2. 6.9.4.1.3.2 Shunt Capacitance
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
            1. 6.9.4.1.6.1 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Module and Peripheral Clocks Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  ATL
          1. 6.9.5.1.1 ATL_PCLK Timing Requirements
          2. 6.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.9.5.2  VPFE
        3. 6.9.5.3  CPSW2G
          1. 6.9.5.3.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.3.2 CPSW2G RMII Timings
            1. 6.9.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.9.5.3.3 CPSW2G RGMII Timings
            1. 6.9.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.9.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 6.9.5.4  CPSW9G
          1. 6.9.5.4.1 CPSW9G MDIO Interface Timings
          2. 6.9.5.4.2 CPSW9G RMII Timings
            1. 6.9.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 6.9.5.4.3 CPSW9G RGMII Timings
            1. 6.9.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 6.9.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 6.9.5.5  CSI-2
        6. 6.9.5.6  DDRSS
        7. 6.9.5.7  DSS
        8. 6.9.5.8  eCAP
          1. 6.9.5.8.1 Timing Requirements for eCAP
          2. 6.9.5.8.2 Switching Characteristics for eCAP
        9. 6.9.5.9  EPWM
          1. 6.9.5.9.1 Timing Requirements for eHRPWM
          2. 6.9.5.9.2 Switching Characteristics for eHRPWM
        10. 6.9.5.10 eQEP
          1. 6.9.5.10.1 Timing Requirements for eQEP
          2. 6.9.5.10.2 Switching Characteristics for eQEP
        11. 6.9.5.11 GPIO
          1. 6.9.5.11.1 GPIO Timing Requirements
          2. 6.9.5.11.2 GPIO Switching Characteristics
        12. 6.9.5.12 GPMC
          1. 6.9.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.9.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.9.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.9.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.9.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.9.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.9.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.9.5.12.4 GPMC0 IOSET
        13. 6.9.5.13 HyperBus
          1. 6.9.5.13.1 Timing Requirements for HyperBus
          2. 6.9.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 6.9.5.14 I2C
        15. 6.9.5.15 I3C
        16. 6.9.5.16 MCAN
        17. 6.9.5.17 MCASP
        18. 6.9.5.18 MCSPI
          1. 6.9.5.18.1 MCSPI — Master Mode
          2. 6.9.5.18.2 MCSPI — Slave Mode
        19. 6.9.5.19 MMCSD
          1. 6.9.5.19.1 MMC0 - eMMC Interface
            1. 6.9.5.19.1.1 Legacy SDR Mode
            2. 6.9.5.19.1.2 High Speed SDR Mode
            3. 6.9.5.19.1.3 High Speed DDR Mode
            4. 6.9.5.19.1.4 HS200 Mode
          2. 6.9.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 6.9.5.19.2.1 Default Speed Mode
            2. 6.9.5.19.2.2 High Speed Mode
            3. 6.9.5.19.2.3 UHS–I SDR12 Mode
            4. 6.9.5.19.2.4 UHS–I SDR25 Mode
            5. 6.9.5.19.2.5 UHS–I SDR50 Mode
            6. 6.9.5.19.2.6 UHS–I DDR50 Mode
            7. 6.9.5.19.2.7 UHS–I SDR104 Mode
        20. 6.9.5.20 CPTS
          1. 6.9.5.20.1 CPTS Timing Requirements
          2. 6.9.5.20.2 CPTS Switching Characteristics
        21. 6.9.5.21 OSPI
          1. 6.9.5.21.1 OSPI PHY Mode
            1. 6.9.5.21.1.1 OSPI With Data Training
              1. 6.9.5.21.1.1.1 OSPI Switching Characteristics – Data Training
            2. 6.9.5.21.1.2 OSPI Without Data Training
              1. 6.9.5.21.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.9.5.21.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.9.5.21.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.9.5.21.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 6.9.5.21.2 OSPI Tap Mode
            1. 6.9.5.21.2.1 OSPI Tap SDR Timing
            2. 6.9.5.21.2.2 OSPI Tap DDR Timing
        22. 6.9.5.22 PCIE
        23. 6.9.5.23 Timers
          1. 6.9.5.23.1 Timing Requirements for Timers
          2. 6.9.5.23.2 Switching Characteristics for Timers
        24. 6.9.5.24 UART
          1. 6.9.5.24.1 Timing Requirements for UART
          2. 6.9.5.24.2 UART Switching Characteristics
        25. 6.9.5.25 USB
      6. 6.9.6 Emulation and Debug
        1. 6.9.6.1 Trace
        2. 6.9.6.2 JTAG
          1. 6.9.6.2.1 JTAG Electrical Data and Timing
            1. 6.9.6.2.1.1 JTAG Timing Requirements
            2. 6.9.6.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A72
      2. 7.2.2 Arm Cortex-R5F
      3. 7.2.3 DSP C71x
      4. 7.2.4 DSP C66x
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 GPU
      2. 7.3.2 D5520MP2
      3. 7.3.3 VXE384MP2
    4. 7.4 Other Subsystems
      1. 7.4.1 MSMC
      2. 7.4.2 NAVSS
        1. 7.4.2.1 NAVSS0
        2. 7.4.2.2 MCU_NAVSS
      3. 7.4.3 PDMA Controller
      4. 7.4.4 Power Supply
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  ATL
        3. 7.4.5.3  CSI
          1. 7.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 7.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 7.4.5.4  CPSW2G
        5. 7.4.5.5  CPSW9G
        6. 7.4.5.6  DCC
        7. 7.4.5.7  DDRSS
        8. 7.4.5.8  DSS
          1. 7.4.5.8.1 DSI
          2. 7.4.5.8.2 eDP
        9. 7.4.5.9  VPFE
        10. 7.4.5.10 eCAP
        11. 7.4.5.11 EPWM
        12. 7.4.5.12 ELM
        13. 7.4.5.13 ESM
        14. 7.4.5.14 eQEP
        15. 7.4.5.15 GPIO
        16. 7.4.5.16 GPMC
        17. 7.4.5.17 Hyperbus
        18. 7.4.5.18 I2C
        19. 7.4.5.19 I3C
        20. 7.4.5.20 MCAN
        21. 7.4.5.21 MCASP
        22. 7.4.5.22 MCRC Controller
        23. 7.4.5.23 MCSPI
        24. 7.4.5.24 MMC/SD
        25. 7.4.5.25 OSPI
        26. 7.4.5.26 PCIE
        27. 7.4.5.27 SerDes
        28. 7.4.5.28 WWDT
        29. 7.4.5.29 Timers
        30. 7.4.5.30 UART
        31. 7.4.5.31 USB
        32. 7.4.5.32 UFS
  9. 8 Applications and Implementation
    1. 8.1 Power Supply Mapping
    2. 8.2 Device Connection and Layout Fundamentals
      1. 8.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.2.1.1 Power Distribution Network Implementation Guidance
      2. 8.2.2 External Oscillator
      3. 8.2.3 JTAG and EMU
      4. 8.2.4 Reset
      5. 8.2.5 Unused Pins
      6. 8.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 8.3 Peripheral- and Interface-Specific Design Information
      1. 8.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.3.2.1 No Loopback and Internal Pad Loopback
        2. 8.3.2.2 External Board Loopback
        3. 8.3.2.3 DQS (only available in Octal Flash devices)
      3. 8.3.3 SERDES REFCLK Design Guidelines
      4. 8.3.4 USB VBUS Design Guidelines
      5. 8.3.5 System Power Supply Monitor Design Guidelines
      6. 8.3.6 High Speed Differential Signal Routing Guidance
      7. 8.3.7 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALF|827
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.24.1 MAIN Domain

Table 5-95 MCASP0 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP0_ACLKRMCASP Receive Bit ClockIOAE27
MCASP0_ACLKXMCASP Transmit Bit ClockIOAB26
MCASP0_AFSRMCASP Receive Frame SyncIOAD26
MCASP0_AFSXMCASP Transmit Frame SyncIOAB25
MCASP0_AXR0MCASP Serial Data (Input/Output)IOAF28
MCASP0_AXR1MCASP Serial Data (Input/Output)IOAE28
MCASP0_AXR2MCASP Serial Data (Input/Output)IOAD25
MCASP0_AXR3MCASP Serial Data (Input/Output)IOAC29
MCASP0_AXR4MCASP Serial Data (Input/Output)IOAE26
MCASP0_AXR5MCASP Serial Data (Input/Output)IOAC28
MCASP0_AXR6MCASP Serial Data (Input/Output)IOAC27
MCASP0_AXR7MCASP Serial Data (Input/Output)IOAJ28
MCASP0_AXR8MCASP Serial Data (Input/Output)IOAH27
MCASP0_AXR9MCASP Serial Data (Input/Output)IOAH29
MCASP0_AXR10MCASP Serial Data (Input/Output)IOAG28
MCASP0_AXR11MCASP Serial Data (Input/Output)IOAG27
MCASP0_AXR12MCASP Serial Data (Input/Output)IOAH28
MCASP0_AXR13MCASP Serial Data (Input/Output)IOAB24
MCASP0_AXR14MCASP Serial Data (Input/Output)IOAB29
MCASP0_AXR15MCASP Serial Data (Input/Output)IOAB28
Table 5-96 MCASP1 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP1_ACLKRMCASP Receive Bit ClockIOAD27
MCASP1_ACLKXMCASP Transmit Bit ClockIOAB27
MCASP1_AFSRMCASP Receive Frame SyncIOAC25
MCASP1_AFSXMCASP Transmit Frame SyncIOAA28
MCASP1_AXR0MCASP Serial Data (Input/Output)IOAE29
MCASP1_AXR1MCASP Serial Data (Input/Output)IOAD28
MCASP1_AXR2MCASP Serial Data (Input/Output)IOAD29
MCASP1_AXR3MCASP Serial Data (Input/Output)IOAC26
MCASP1_AXR4MCASP Serial Data (Input/Output)IOAA24
MCASP1_AXR5MCASP Serial Data (Input/Output)IOY24
MCASP1_AXR6MCASP Serial Data (Input/Output)IOAA25
MCASP1_AXR7MCASP Serial Data (Input/Output)IOAG26
MCASP1_AXR8MCASP Serial Data (Input/Output)IOAF27
MCASP1_AXR9MCASP Serial Data (Input/Output)IOAF26
MCASP1_AXR10MCASP Serial Data (Input/Output)IOAD27
MCASP1_AXR11MCASP Serial Data (Input/Output)IOAC25
Table 5-97 MCASP2 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP2_ACLKRMCASP Receive Bit ClockIOAA27
MCASP2_ACLKXMCASP Transmit Bit ClockIOAA29
MCASP2_AFSRMCASP Receive Frame SyncIOY26
MCASP2_AFSXMCASP Transmit Frame SyncIOAA26
MCASP2_AXR0MCASP Serial Data (Input/Output)IOAE25
MCASP2_AXR1MCASP Serial Data (Input/Output)IOAF29
MCASP2_AXR2MCASP Serial Data (Input/Output)IOAG29
MCASP2_AXR3MCASP Serial Data (Input/Output)IOY25
MCASP2_AXR4MCASP Serial Data (Input/Output)IOY26
MCASP2_AXR5MCASP Serial Data (Input/Output)IOAA27
Table 5-98 MCASP3 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP3_ACLKRMCASP Receive Bit ClockIOAF23
MCASP3_ACLKXMCASP Transmit Bit ClockIOAG20
MCASP3_AFSRMCASP Receive Frame SyncIOAD23
MCASP3_AFSXMCASP Transmit Frame SyncIOAD21
MCASP3_AXR0MCASP Serial Data (Input/Output)IOAD20
MCASP3_AXR1MCASP Serial Data (Input/Output)IOAE20
MCASP3_AXR2MCASP Serial Data (Input/Output)IOAJ20
MCASP3_AXR3MCASP Serial Data (Input/Output)IOAJ21
Table 5-99 MCASP4 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP4_ACLKRMCASP Receive Bit ClockIOAG25
MCASP4_ACLKXMCASP Transmit Bit ClockIOAE21
MCASP4_AFSRMCASP Receive Frame SyncIOAH26
MCASP4_AFSXMCASP Transmit Frame SyncIOAH21
MCASP4_AXR0MCASP Serial Data (Input/Output)IOAG21
MCASP4_AXR1MCASP Serial Data (Input/Output)IOAC21
MCASP4_AXR2MCASP Serial Data (Input/Output)IOY23
MCASP4_AXR3MCASP Serial Data (Input/Output)IOAF21
Table 5-100 MCASP5 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP5_ACLKRMCASP Receive Bit ClockIOAD19
MCASP5_ACLKXMCASP Transmit Bit ClockIOAB23
MCASP5_AFSRMCASP Receive Frame SyncIOAD18
MCASP5_AFSXMCASP Transmit Frame SyncIOAC22
MCASP5_AXR0MCASP Serial Data (Input/Output)IOAJ22
MCASP5_AXR1MCASP Serial Data (Input/Output)IOAH22
MCASP5_AXR2MCASP Serial Data (Input/Output)IOAD19
MCASP5_AXR3MCASP Serial Data (Input/Output)IOAD18
Table 5-101 MCASP6 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP6_ACLKRMCASP Receive Bit ClockIOAH23
MCASP6_ACLKXMCASP Transmit Bit ClockIOAC23
MCASP6_AFSRMCASP Receive Frame SyncIOAD22
MCASP6_AFSXMCASP Transmit Frame SyncIOAG22
MCASP6_AXR0MCASP Serial Data (Input/Output)IOAF22
MCASP6_AXR1MCASP Serial Data (Input/Output)IOAJ23
MCASP6_AXR2MCASP Serial Data (Input/Output)IOAH23
MCASP6_AXR3MCASP Serial Data (Input/Output)IOAD22
Table 5-102 MCASP7 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP7_ACLKRMCASP Receive Bit ClockIOAC24
MCASP7_ACLKXMCASP Transmit Bit ClockIOAF24
MCASP7_AFSRMCASP Receive Frame SyncIOAE24
MCASP7_AFSXMCASP Transmit Frame SyncIOAJ24
MCASP7_AXR0MCASP Serial Data (Input/Output)IOAG24
MCASP7_AXR1MCASP Serial Data (Input/Output)IOAD24
MCASP7_AXR2MCASP Serial Data (Input/Output)IOAC24
MCASP7_AXR3MCASP Serial Data (Input/Output)IOAE24
Table 5-103 MCASP8 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP8_ACLKRMCASP Receive Bit ClockIOAH24
MCASP8_ACLKXMCASP Transmit Bit ClockIOAE22
MCASP8_AFSRMCASP Receive Frame SyncIOAE23
MCASP8_AFSXMCASP Transmit Frame SyncIOAG23
MCASP8_AXR0MCASP Serial Data (Input/Output)IOAF23
MCASP8_AXR1MCASP Serial Data (Input/Output)IOAD23
MCASP8_AXR2MCASP Serial Data (Input/Output)IOAH24
MCASP8_AXR3MCASP Serial Data (Input/Output)IOAE23
Table 5-104 MCASP9 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP9_ACLKRMCASP Receive Bit ClockIOAJ27
MCASP9_ACLKXMCASP Transmit Bit ClockIOAJ25
MCASP9_AFSRMCASP Receive Frame SyncIOAJ26
MCASP9_AFSXMCASP Transmit Frame SyncIOAH25
MCASP9_AXR0MCASP Serial Data (Input/Output)IOAG25
MCASP9_AXR1MCASP Serial Data (Input/Output)IOAH26
MCASP9_AXR2MCASP Serial Data (Input/Output)IOAJ27
MCASP9_AXR3MCASP Serial Data (Input/Output)IOAJ26
Table 5-105 MCASP10 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP10_ACLKRMCASP Receive Bit ClockIOY28
MCASP10_ACLKXMCASP Transmit Bit ClockIOU23
MCASP10_AFSRMCASP Receive Frame SyncIOV23
MCASP10_AFSXMCASP Transmit Frame SyncIOU26
MCASP10_AXR0MCASP Serial Data (Input/Output)IOV28
MCASP10_AXR1MCASP Serial Data (Input/Output)IOV29
MCASP10_AXR2MCASP Serial Data (Input/Output)IOU29
MCASP10_AXR3MCASP Serial Data (Input/Output)IOU25
MCASP10_AXR4MCASP Serial Data (Input/Output)IOV25
MCASP10_AXR5MCASP Serial Data (Input/Output)IOW27
MCASP10_AXR6MCASP Serial Data (Input/Output)IOW29
MCASP10_AXR7MCASP Serial Data (Input/Output)IOW26
Table 5-106 MCASP11 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
MCASP11_ACLKRMCASP Receive Bit ClockIOW23
MCASP11_ACLKXMCASP Transmit Bit ClockIOV27
MCASP11_AFSRMCASP Receive Frame SyncIOW28
MCASP11_AFSXMCASP Transmit Frame SyncIOU28
MCASP11_AXR0MCASP Serial Data (Input/Output)IOU27
MCASP11_AXR1MCASP Serial Data (Input/Output)IOU24
MCASP11_AXR2MCASP Serial Data (Input/Output)IOR23
MCASP11_AXR3MCASP Serial Data (Input/Output)IOT23
MCASP11_AXR4MCASP Serial Data (Input/Output)IOY29
MCASP11_AXR5MCASP Serial Data (Input/Output)IOY27
MCASP11_AXR6MCASP Serial Data (Input/Output)IOW24
MCASP11_AXR7MCASP Serial Data (Input/Output)IOW25