SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
RMII4 | tsu(rxdV-ref_clkH) | Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK rising edge | 4 | ns | |
tsu(crs_dvV-ref_clkH) | Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK rising edge | 4 | ns | ||
tsu(rx_erV-ref_clkH) | Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK rising edge | 4 | ns | ||
RMII5 | th(ref_clkH-rxdV) | Hold time, RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK rising edge | 2 | ns | |
th(ref_clkH-crs_dvV) | Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK rising edge | 2 | ns | ||
th(ref_clkH-rx_erV) | Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK rising edge | 2 | ns |
Section 6.9.5.3.2.3, and Figure 6-44 present switching characteristics for CPSW2G RMII Transmit.