SLASF54 January   2023 DRV2901

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Block Diagrams
    2. 7.2 Feature Description
      1. 7.2.1 Error Reporting
      2. 7.2.2 Device Reset
      3. 7.2.3 Device Protection System
        1. 7.2.3.1 Overcurrent (OC) Protection With Current Limiting and Overload Detection
        2. 7.2.3.2 Overtemperature Protection
        3. 7.2.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. 9 Power Supply Recommendations
    1. 9.1 System Power-up/power-down Sequence
      1. 9.1.1 Powering Up
      2. 9.1.2 Powering Down
    2. 9.2 System Design Recommendations
      1. 9.2.1 VDD Pin
      2. 9.2.2 VREG Pin
      3. 9.2.3 OTW Pin
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

RL= 6 Ω, FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified.
PARAMETERTEST CONDITIONSDRV2900UNIT
MINTYPMAX
Internal Voltage Regulator and Current Consumption
VREGVoltage regulator, only used as a reference nodeVDD = 12 V2.953.33.65V
IVDDVDD supply currentOperating, 50% duty cycle10mA
Idle, reset mode6
IGVDD_XGate supply current per half-bridge50% duty cycle8mA
Reset mode0.3
IPVDD_XHalf-bridge idle current50% duty cycle, without output filter or load15mA
Reset mode, no switching500μA
Output Stage MOSFETs
RDSon,LSDrain-to-source resistance, LSTJ = 25°C, includes metallization resistance, GVDD = 12 V90mΩ
RDSon,HSDrain-to-source resistance, HSTJ = 25°C, includes metallization resistance, GVDD = 12 V90mΩ
I/O Protection
Vuvp,GUndervoltage protection limit, GVDD_X8.5V
Vuvp,hyst (1)400mV
OTW(1)Overtemperature warning115125135°C
OTWHYST (1)Temperature drop needed below OTW temp. for OTW to be inactive after the OTW event25°C
OTE(1)Overtemperature error145155165°C
OTE-OTWdifferential (1)OTE-OTW differential25°C
OTEHYST (1)A reset needs to occur for SD for be released following an OTE event.25°C
OLPCOverload protection counterFPWM = 384 kHz1.3ms
IOCOvercurrent limit protectionResistor—programmable, nominal, ROCP = 22 kΩ12A
IOCTOvercurrent response timeTime from application of short condition to Hi-Z of affected 1/2 bridge250ns
ROCPOC programming resistor rangeResistor tolerance = 5%2269kΩ
RPDInternal pulldown resistor at the output of each half-bridgeConnected when RESET is active to provide bootstrap capacitor charge. Not used in SE mode1.0kΩ
Static Digital Specifications
VIHHigh-level input voltagePWM_A, PWM_B, RESET_AB2V
VILLow-level input voltage0.8V
LeakageInput leakage current-100100μA
OTW/SHUTDOWN (SD)
RINT_PUInternal pullup resistance, OTW to VREG, SD to VREG202635kΩ
VOHHigh-level output voltageInternal pullup resistor2.953.33.65V
External pullup of 4.7 kΩ to 5 V4.55
VOLLow-level output voltageIO = 4 mA0.20.4V
FANOUTDevice fanout OTW, SDNo external pullup30Devices
(1) Specified by design